Multilayer ceramic capacitor, method of fabrication thereof and circuit board having electronic component mounted thereon

Patent metadata

Field	Value
Publication number	US-10163568-B2
Application number	US-201715445163-A
Country	US
Kind code	B2
Filing date	Feb 28, 2017
Priority date	Mar 28, 2013
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other, a plurality of internal electrodes having the dielectric layer interposed therebetween, electrode layers formed on the first and second end surfaces of the ceramic body and electrically connected to the plurality of internal electrodes, and an impact absorption layer formed on the electrode layer so that an edge thereof is exposed.

First claim

What is claimed is:

1. A multilayer ceramic capacitor comprising:
a ceramic body including a plurality of dielectric layers;
a plurality of internal electrodes having the dielectric layers interposed therebetween;
an electrode layer formed on a surface of the ceramic body and electrically connected to the plurality of internal electrodes;
an outer electrode layer formed on the electrode layer; and
an impact absorption layer formed between the electrode layer and the outer electrode layer and including a base resin,
wherein the outer electrode layer directly contacts the electrode layer,
wherein the outer electrode layer covers an entirety of the impact absorption layer and an edge of the electrode layer, and
wherein the outer electrode layer extends beyond the edge of the electrode layer.

2. The multilayer ceramic capacitor of claim 1 , wherein the ceramic body has first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other, and the electrode layer and the impact absorption layer extend from the first and second end surfaces to the first and second main surfaces or the first and second side surfaces of the ceramic body.

3. The multilayer ceramic capacitor of claim 2 , wherein when a length of the electrode layers formed on the first and second main surfaces or the first and second side surfaces of the ceramic body is B 1 , and a length of the impact absorption layer formed on the first and second main surfaces or the first and second side surfaces of the ceramic body is B 2 , 0.05≤B 2 /B 1 <0.95 is satisfied.

4. The multilayer ceramic capacitor of claim 1 , wherein the outer electrode layer is a plating layer.

5. The multilayer ceramic capacitor of claim 4 , wherein the plating layer is formed so as to cover an edge of the electrode layer.

6. The multilayer ceramic capacitor of claim 1 , wherein the electrode layer is a sintered type electrode.

7. The multilayer ceramic capacitor of claim 1 , wherein the impact absorption layer includes a thermosetting polymer.

8. The multilayer ceramic capacitor of claim 1 , wherein the outer electrode layer covers an entirety of the impact absorption layer and the electrode layer.

9. A circuit board having an electronic component mounted thereon, the circuit board comprising:
a printed circuit board having first and second electrode pads thereon; and
a multilayer ceramic capacitor installed on the printed circuit board,
wherein the multilayer ceramic capacitor includes: a ceramic body including a plurality of dielectric layers; a plurality of internal electrodes having the dielectric layers interposed therebetween; an electrode layer formed on a surface of the ceramic body and electrically connected to the plurality of internal electrodes; an outer electrode layer formed on the electrode layer; and an impact absorption layer formed between the electrode layer and the outer electrode layer and including a base resin, and wherein the outer electrode layer directly contacts the electrode layer,
wherein the outer electrode layer covers an entirety of the impact absorption layer and an edge of the electrode layer, and
wherein the outer electrode layer extends beyond the edge of the electrode layer.

10. The circuit board of claim 9 , wherein the outer electrode layer is a plating layer.

11. The circuit board of claim 10 , wherein the plating layer is formed so as to cover an edge of the electrode layer.

Assignees

• Samsung Electro Mech
• Samsung Electro Mech

Inventors

• Park Myung Jun
• Park Kyu Sik
• Lee Young Sook

Classifications

• H01G4/12 Primary

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H05K1/111

  Pads for surface mounting, e.g. lay-out · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title