Semiconductor package including semiconductor chips

Patent metadata

Field	Value
Publication number	US-11569193-B2
Application number	US-202117223614-A
Country	US
Kind code	B2
Filing date	Apr 6, 2021
Priority date	Oct 26, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A semiconductor package may include a semiconductor chip on a package substrate. The semiconductor package may include a plurality of conductive connections connecting the semiconductor chip to the package substrate may be disposed, a plurality of towers which are apart from one another and each include a plurality of memory chips may be disposed, wherein a lowermost memory chip of each of the plurality of towers overlaps the semiconductor chip from a top-down view. The semiconductor package further includes a plurality of adhesive layers be attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate;
a plurality of first conductive connections connecting the semiconductor chip to the package substrate;
a first spacer and a second spacer on the package substrate, each of the first spacer and the second spacer horizontally spaced apart from the semiconductor chip;
a first tower and a second tower each including a plurality of memory chips, a first memory chip disposed at a lowermost end of the first tower and vertically overlapping the semiconductor chip and the first spacer from a top-down view, and a second memory chip disposed at a lowermost end of the second tower and vertically overlapping the semiconductor chip and the second spacer from a top-down view; and
a plurality of first adhesive layers including an adhesive layer attached between the first memory chip and the semiconductor chip, an adhesive layer attached between the first memory chip and the first spacer, an adhesive layer attached between the second memory chip and the semiconductor chip, and an adhesive layer attached between the second memory chip and the second spacer.

2. The semiconductor package of claim 1 , wherein
a horizontal width of the package substrate is a first width,
a horizontal width of an overlap region between the first memory chip and the semiconductor chip is a second width, and
the second width is less than half of the first width.

3. The semiconductor package of claim 2 , wherein the second width is about 0.2 mm or more.

4. The semiconductor package of claim 2 , wherein
the package substrate comprises a first side surface and a second side surface opposite to the first side surface,
a minimum horizontal distance between any of the plurality of memory chips and an extension line which passes through the first side surface and is perpendicular to a top surface of the package substrate is a third width, and
the third width is greater than 0 mm and less than or equal to the second width.

5. The semiconductor package of claim 4 , wherein the second width is greater than or equal to the third width.

6. The semiconductor package of claim 1 , wherein
the semiconductor chip comprises a plurality of pads, and
each of the first memory chip and the second memory chip overlaps an upper portion of at least one of the plurality of pads, from a top-down view.

7. The semiconductor package of claim 1 , wherein at least some of the plurality of first conductive connections extend to be within an inner boundary formed by the plurality of first adhesive layers.

8. The semiconductor package of claim 1 , wherein the plurality of first adhesive layers comprise a direct adhesive film (DAF) or a film over wire (FOW).

9. The semiconductor package of claim 1 , wherein
the package substrate comprises a first side surface and a second side surface opposite to the first side surface,
the plurality of memory chips of the first tower are stacked sequentially and in an upward staircase manner in a direction toward the first side surface, and
the plurality of memory chips of the second tower are stacked sequentially and in an upward staircase manner in a direction toward the second side surface.

10. The semiconductor package of claim 1 , wherein
a side surface of the first memory chip and a side surface of the first spacer are coplanar with each other, and
a side surface of the second memory chip and a side surface of the second spacer are coplanar with each other.

11. The semiconductor package of claim 1 , wherein the semiconductor chip and top surfaces of the first and second spacers are coplanar with each other.

12. The semiconductor package of claim 1 , wherein the semiconductor chip comprises a buffer chip, an interposer chip, a controller chip, a logic chip, or a combination thereof.

13. The semiconductor package of claim 1 , further comprising a plurality of second conductive connections connecting the plurality of memory chips to the semiconductor chip.

14. The semiconductor package of claim 1 , further comprising a plurality of second adhesive layers disposed between pairs of the plurality of memory chips,
wherein a thickness of each of the plurality of first adhesive layers is thicker than a thickness of each of the plurality of second adhesive layers.

15. A semiconductor package comprising:
a package substrate;
a semiconductor chip on the package substrate;
a plurality of conductive connections connecting the semiconductor chip to the package substrate;
a plurality of towers apart from one another, each including a plurality of memory chips, a lowermost memory chip of each of the plurality of towers overlapping the semiconductor chip from a top-down view; and
a plurality of adhesive layers attached between the lowermost memory chip of each of the plurality of towers and the semiconductor chip.

16. The semiconductor package of claim 15 , wherein the plurality of conductive connections extend to be within an inner boundary formed by the plurality of adhesive layers.

17. The semiconductor package of claim 15 , wherein:
the plurality of towers includes at least a first tower, wherein a bottom-most surface of the first tower overlaps the semiconductor chip and extends beyond an outermost edge of a top surface of the semiconductor chip.

18. The semiconductor package of claim 15 , wherein:
the package substrate comprises a first side surface and a second side surface opposite to the first side surface,
a plurality of memory chips of a first tower of the plurality of towers are stacked sequentially and in an upward staircase manner in a direction toward the first side surface, and
a plurality of memory chips of a second tower of the plurality of towers are stacked sequentially and in an upward staircase manner in a direction toward the second side surface.

19. A semiconductor package comprising:
a package substrate;
a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip on the package substrate, horizontally spaced apart from each other;
a plurality of first conductive connections connecting the first to third semiconductor chips to the package substrate;
a first tower and a second tower each including a plurality of memory chips, a first memory chip disposed at a lowermost end of the first tower overlapping the first semiconductor chip and the second semiconductor chip from a top-down view, and a second memory chip disposed at a lowermost end of the second tower overlapping the first semiconductor chip and the third semiconductor chip from a top-down view; and
a plurality of first adhesive layers attached respectively between the first memory chip and the first semiconductor chip, between the first memory chip and the second semiconductor chip, between the second memory chip and the first semiconductor chip, and between the second memory chip and the third semiconductor chip.

20. The semiconductor package of claim 19 , wherein
the package substrate comprises a first side surface and a second side surface opposite to the first side surface,
the plurality of memory chips of the first tower are stacked sequentially, some of the plurality of memory chips of the first tower are stacked sequentially in an upward staircase manner in a direction toward the first side surface, and some other memory chips of the plurality of memory chips of the first tower are stacked sequentially in an upward staircase manner in a direction toward the second side surface,

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Hyungu
• Sung Jaekyu

Classifications

• H01L24/32

  Electricity · mapped topic

• H01L2224/49107

  Electricity · mapped topic

• H01L2924/1435

  Electricity · mapped topic

• H01L2224/32145

  Electricity · mapped topic

• H01L24/48

  Electricity · mapped topic