Semiconductor device assemblies including multiple shingled stacks of semiconductor dies

Patent metadata

Field	Value
Publication number	US-10522507-B2
Application number	US-201916383903-A
Country	US
Kind code	B2
Filing date	Apr 15, 2019
Priority date	Nov 8, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

A semiconductor device assembly includes a substrate having a plurality of external connections, a first shingled stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second shingled stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first shingled stack and the second shingled stack.

First claim

We claim:

1. A method of making a memory device, comprising:
providing a substrate;
stacking a first plurality of semiconductor dies on the substrate in a first shingled stack;
stacking a second plurality of semiconductor dies on the substrate in a second shingled stack;
wirebonding, subsequent to stacking the first and second shingled stacks, the first and second pluralities of semiconductor dies to the substrate; and
providing an encapsulant to at least partially encapsulate the substrate, the first shingled stack and the second shingled stack,
wherein the first shingled stack of semiconductor dies comprise memory dies corresponding to a first memory channel of the memory device, and
wherein the second shingled stack of semiconductor dies comprise memory dies corresponding to a second memory channel of the memory device.

2. The method of claim 1 , wherein the wirebonding is performed in a single operation uninterrupted by any stacking.

3. The method of claim 2 , wherein:
the first plurality of semiconductor dies is stacked directly over a first location on the substrate, and
the second plurality of semiconductor dies is stacked directly over a second location on the substrate.

4. The method of claim 2 , further comprising:
stacking a third plurality of semiconductor dies in a third shingled stack;
stacking a fourth plurality of semiconductor dies in a fourth shingled stack; and
wirebonding, subsequent to stacking the third and fourth shingled stacks, the third and fourth pluralities of semiconductor dies to the substrate.

5. The method of claim 4 , wherein wirebonding the first and second pluralities of semiconductor dies to the substrate is performed subsequent to stacking the third and fourth shingled stacks.

6. The method of claim 1 , wherein the substrate includes a plurality of external connections, and wherein wirebonding the first plurality of semiconductor dies to the substrate comprises electrically coupling the first plurality of semiconductor dies to a first subset of the plurality of external connections.

7. The method of claim 6 , wherein wirebonding the second plurality of semiconductor dies to the substrate comprises electrically coupling the second plurality of semiconductor dies to a second subset of the plurality of external connections.

8. The method of claim 1 , wherein the first shingled stack and the second shingled stack include a same number of semiconductor dies.

9. The method of claim 8 , wherein the number is one of two, four, eight, or sixteen.

Assignees

• Micron Technology Inc

Inventors

• Ng Hong Wan
• Singh Akshay N

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/231

  the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure · CPC title