Memory devices with controllers under memory packages and associated systems and methods

Patent metadata

Field	Value
Publication number	US-9627367-B2
Application number	US-201414550243-A
Country	US
Kind code	B2
Filing date	Nov 21, 2014
Priority date	Nov 21, 2014
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Memory devices with controllers under stacks of memory packages and associated systems and methods are disclosed herein. In one embodiment, a memory device is configured to couple to a host and can include a substrate, a stack of memory packages, and a controller positioned between the stack and the substrate. The controller can manage data stored by the memory packages based on commands from the host.

First claim

What is claimed is:

1. A memory device, comprising:
a package substrate;
a stack structure including
a stacked plurality of memory packages with semiconductor dies, wherein the stacked plurality of memory packages is attached to the package substrate, and
a controller attached to the package substrate and positioned between the stacked plurality of memory packages and the package substrate, wherein the controller is configured to manage each of the memory packages; and

an encapsulant attached to a periphery of the package substrate surrounding the stack structure, and the encapsulant encapsulating the stack of memory packages.

2. The memory device of claim 1 wherein the controller is configured to manage data transfer to and from each of the memory packages.

3. The memory device of claim 1 wherein the package substrate includes a plurality of first bond pads and a plurality of second bond pads, and wherein the memory device further includes
a plurality of first wire bonds that couple the plurality of first bond pads to the memory packages; and
a plurality of second wire bonds that couple the plurality of second bond pads to the controller.

4. The memory device of claim 1 wherein each of the memory packages includes a substrate, a plurality of memory semiconductor dies, and a package casing at least partially encapsulating the memory semiconductor dies.

5. The memory device of claim 1 wherein each of the memory packages is a multichip package electrically connected to the package substrate.

6. The memory device of claim 1 wherein each of the memory packages is attached to an adjacent one of the memory packages by a die-attach adhesive.

7. The memory device of claim 1 wherein the stacked plurality of memory packages includes a first memory package and a second memory package, wherein the first memory package is attached to the package substrate, and the second memory package is attached to the first memory package by a die-attach adhesive.

8. The memory device of claim 1 wherein the memory packages comprises flash memory and includes NAND memory and/or NOR memory.

9. The memory device of claim 1 wherein each of the memory packages is a NAND package without an embedded controller.

10. The memory device of claim 1 wherein the controller is positioned between a bottom one of the memory packages in the stack and the package substrate.

11. The memory device of claim 1 , further comprising a spacer between the stack of memory packages and the package substrate, and wherein the spacer is spaced laterally apart from the controller.

12. The memory device of claim 1 wherein the controller is configured to command the memory packages to read data, erase data, and/or write data.

13. The memory device of claim 1 wherein the controller is positioned outside each of the memory packages.

14. A multimedia device configured to couple to a host, comprising:
an interposer;
a stack of multichip memory packages electrically coupled to the interposer, wherein the stack of multichip memory packages is mounted on the interposer;
a multimedia controller die attached to the interposer and positioned between the stack of multichip memory packages and the interposer, wherein the multimedia controller die is configured to manage data transfer between the host and each of the multichip memory packages; and
an encapsulant encapsulating the stack of multichip memory packages and attached to the interposer.

15. The multimedia device of claim 14 wherein the multimedia controller die is coupled to each of the memory packages.

16. The multimedia device of claim 14 wherein the multimedia controller die is configured to provide error correction, block management, wear levelling, and/or physical to logical mapping.

17. The multimedia device of claim 14 wherein the multimedia controller die includes a memory interface coupled to each of the multichip memory packages.

18. The multimedia device of claim 14 wherein each multichip memory package is a NAND package.

19. A method of manufacturing a memory package, the method comprising:
attaching a controller to a package substrate;
attaching a first memory package to the package substrate such that the controller is positioned between the first memory package and the package substrate;
attaching a second memory package to the first memory package; and
encapsulating the first and second memory packages such that an encapsulant is attached to the package substrate and surrounds the controller and the first and second memory packages.

20. The method of claim 19 , further comprising
wirebonding the controller to the package substrate; and
wirebonding the first and second memory packages to the package substrate.

21. The method of claim 19 , further comprising flowing encapsulant into a cavity between the package substrate and the first memory package such that the encapsulant at least partially encapsulates the controller.

22. The method of claim 19 wherein attaching the first memory package to the package substrate includes attaching the first memory package to the package substrate such that most of the controller is positioned directly between the first memory package and the package substrate.

23. The method of claim 19 wherein attaching the first memory package to the package substrate includes mounting the first memory package to the package substrate such that wire bonds coupling the controller to the package substrate are directly between the first memory package and the package substrate.

24. The method of claim 19 wherein the controller is a multimedia controller and the first and second memory packages are NAND packages and/or NOR packages.

25. The method of claim 19 , further comprising testing the first and second packages to identify know good packages prior to attaching the first and second memory packages to the package substrate.

26. The method of claim 19 , further comprising stacking additional memory packages on the second memory package before encapsulating the first and second memory packages and the additional packages.

27. The memory device of claim 1 wherein the stacked plurality of memory packages, the controller, and the encapsulant are mounted on the package substrate.

28. The memory device of claim 1 wherein the controller is positioned directly between portions of the encapsulant.

29. The multimedia device of claim 14 wherein the multimedia controller die is positioned directly between portions of the encapsulant.

Assignees

• Micron Technology Inc

Inventors

• Ye Seng Kim
• Ng Hong Wan

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/656

  Fan-in layouts · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title