Semiconductor package having supporting plate and method of forming the same

Patent metadata

Field	Value
Publication number	US-9412720-B2
Application number	US-201414184951-A
Country	US
Kind code	B2
Filing date	Feb 20, 2014
Priority date	Aug 31, 2011
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A semiconductor package may include a packaging substrate, a first semiconductor chip on the packaging substrate, and a support plate on the packaging substrate. The support plate may be spaced apart from the first semiconductor chip in a direction parallel with respect to a surface of the packaging substrate. A second semiconductor chip may be provided on the first semiconductor chip and on the support plate so that the first semiconductor chip is between the second semiconductor chip and the packaging substrate and so that the support plate is between the second semiconductor chip and the packaging substrate. An adhesion layer may bond the second semiconductor chip to the first semiconductor chip and may bond the second semiconductor chip to the support plate. In addition, an electrical coupling may be provided between the first semiconductor chip and the packaging substrate.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate, wherein the first semiconductor chip comprises a controller;
a second semiconductor chip on the substrate, wherein the second semiconductor chip comprises a buffer chip;
a chip stack on the first and the second semiconductor chips and having at least one third semiconductor chip;
an adhesion layer between the first semiconductor chip and the chip stack and between the second semiconductor chip and the chip stack;
a first conductive connection, wherein the first conductive connection penetrates the adhesion layer and connects the substrate to the first semiconductor chip, wherein a portion of the first conductive connection is between the first and second semiconductor chips; and
a second conductive connection, wherein the second conductive connection penetrates the adhesion layer and connects the substrate to the second semiconductor chip, wherein a portion of the second conductive connection is between the first and second semiconductor chips; and
a support plate between the substrate and the chip stack, wherein the adhesion layer is directly on the first semiconductor chip, the second semiconductor chip, and the support plate;
wherein the chip stack includes a plurality of third semiconductor chips, wherein the plurality of third semiconductor chips comprises a plurality of memory chips, and wherein a sidewall of the first semiconductor chip is coplanar with a sidewall of a first one of the third semiconductor chips.

2. The semiconductor package according to claim 1 , wherein top surfaces of the first semiconductor chip and the second semiconductor chip are formed at a same horizontal level.

3. The semiconductor package according to claim 2 , wherein the adhesion layer is in direct contact with a top surface of the first semiconductor chip, a top surface of the second semiconductor chip, and a bottom surface of the chip stack.

4. The semiconductor package according to claim 3 , wherein the adhesion layer is in direct contact with the first of the third semiconductor chips, and the first semiconductor chip.

5. The semiconductor package according to claim 2 , wherein the second semiconductor chip has a same thickness as the first semiconductor chip.

6. The semiconductor package according to claim 1 , wherein a sidewall of the second semiconductor chip is coplanar with a sidewall of the first one of the third semiconductor chips.

7. The semiconductor package according to claim 1 , wherein the first of the third semiconductor chips has a greater width than the first semiconductor chip and has a greater width than the second semiconductor chip.

8. The semiconductor package according to claim 7 , wherein each of the third semiconductor chips has a same thickness.

9. The semiconductor package according to claim 1 , wherein at least a portion of the conductive connection is physically located directly between the second semiconductor chip and the chip stack in a direction perpendicular with respect to a surface of the substrate.

10. The semiconductor package according to claim 1 , wherein the conductive connection comprises a wire bond.

11. The semiconductor package of claim 1 wherein the buffer chip is between the controller and the support plate.

12. A semiconductor package, comprising:
a first semiconductor chip on a substrate;
a second semiconductor chip on the substrate, the second semiconductor chip being separate from the first semiconductor chip;
a support plate on the substrate, wherein the second semiconductor chip is between the first semiconductor chip and the support plate;
a chip stack on the first and second semiconductor chips and the support plate and having at least one third semiconductor chip;
an adhesion layer between the first semiconductor chip and the chip stack, between the second semiconductor chip and the chip stack, and between the support plate and the chip stack;
a first conductive connection, wherein the first conductive connection penetrates the adhesion layer and connects the substrate to the first semiconductor chip, wherein a portion of the first conductive connection is between the first and second semiconductor chips; and
a second conductive connection, wherein the second conductive connection penetrates the adhesion layer and connects the substrate to the second semiconductor chip, wherein a portion of the second conductive connection is between the second semiconductor chip and the support plate;
wherein the chip stack includes a plurality of third semiconductor chips, wherein a sidewall of the first semiconductor chip is coplanar with a sidewall of a first one of the third semiconductor chips,
wherein the adhesion layer is in direct contact with the first and second semiconductor chips and the support plate, and
wherein the first conductive connection and the second conductive connection are between the third semiconductor chip and the substrate.

13. The semiconductor package of claim 12 wherein the first semiconductor chip comprises a controller, wherein the second semiconductor chip comprises a buffer chip, and wherein the plurality of third semiconductor chips comprises a plurality of memory chips.

14. The semiconductor package of claim 13 wherein the buffer chip is between the controller and the support plate.

15. The semiconductor package of claim 12 wherein all portions of the first conductive connection and the second conductive connection are in a shadow region of the third semiconductor chip.

16. A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate, wherein the first semiconductor chip comprises a controller;
a second semiconductor chip on the substrate, wherein the second semiconductor chip comprises a buffer chip;
a chip stack on the first and the second semiconductor chips and having at least one third semiconductor chip, wherein the chip stack includes a plurality of third semiconductor chips, wherein a sidewall of the first semiconductor chip is coplanar with a sidewall of a first one of the third semiconductor chips, and wherein the plurality of third semiconductor chips comprises a plurality of memory chips;
an adhesion layer between the first semiconductor chip and the chip stack and between the second semiconductor chip and the chip stack;
a first conductive connection, wherein the first conductive connection penetrates the adhesion layer and connects the substrate to the first semiconductor chip;
a second conductive connection, wherein the second conductive connection penetrates the adhesion layer and connects the substrate to the second semiconductor chip; and
a support plate between the substrate and the chip stack, wherein the adhesion layer is directly on the first semiconductor chip, the second semiconductor chip, and the support plate;
wherein the buffer chip is between the controller and the support plate.

Assignees

• Nam Tae-Duk
• Kim Jin-Ho
• Kim Hyuk-Su
• Kim Hyoung-Suk
• Lee Tae-Young
• Samsung Electronics Co Ltd

Inventors

• Nam Tae-Duk
• Kim Jin-Ho
• Kim Hyuk-Su
• Kim Hyoung-Suk
• Lee Tae-Young

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/738

  between a chip and a stacked discrete passive device · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title