Semiconductor package

Patent metadata

Field	Value
Publication number	US-9355969-B2
Application number	US-201514723721-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Sep 5, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate comprising a ground pad;
a conductive spacer and a first semiconductor chip disposed on the package substrate;
a second semiconductor chip on the conductive spacer and the first semiconductor chip;
a molding unit that covers a top portion of the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and
an electromagnetic interference (EMI) shield that covers the molding unit, side portions of the package substrate, and the exposed second portion of the conductive spacer.

2. The semiconductor package of claim 1 , wherein the second portion of the conductive spacer is electrically connected to the EMI shield.

3. The semiconductor package of claim 1 , wherein a lower surface of the conductive spacer is electrically connected to the ground pad.

4. The semiconductor package of claim 1 , further comprising an adhesive disposed around the ground pad and attaching the conductive spacer to the package substrate.

5. The semiconductor package of claim 1 , wherein a height of the conductive spacer is the same as a height of the first semiconductor chip.

6. The semiconductor package of claim 1 , wherein the package substrate is a double-sided printed circuit board.

7. The semiconductor package of claim 1 , wherein the EMI shield covers an external surface of the molding unit and a side surface of the package substrate.

8. The semiconductor package of claim 1 , wherein a portion of the conductive spacer overlaps the second semiconductor chip.

9. The semiconductor package of claim 1 , wherein the first semiconductor chip is a controller chip.

10. The semiconductor package of claim 1 , further comprising a connection terminal that is attached to a lower surface of the package substrate and electrically connected to another ground pad.

11. A semiconductor package comprising:
a package substrate comprising a ground pad;
a spacer disposed on the package substrate;
a conductive unit on the spacer;
a first semiconductor chip disposed on the package substrate such that the first semiconductor chip is separated from the spacer;
a second semiconductor chip on the spacer and the first semiconductor chip;
a molding unit that covers a top portion of the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the spacer, and a exposes a second portion of the conductive unit; and
an electromagnetic interference (EMI) shield that covers side portions of the package substrate and an external surface of the molding unit.

12. The semiconductor package of claim 11 , wherein the second portion of the conductive unit is covered by the EMI shield.

13. The semiconductor package of claim 11 , further comprising a bonding wire that electrically connects the conductive unit and the ground pad.

14. The semiconductor package of claim 13 , further comprising a ground via that is formed inside the package substrate and electrically connected to the ground pad.

15. The semiconductor package of claim 11 , wherein the EMI shield covers the external surface of the molding unit and a side surface of the package substrate.

16. A semiconductor package, comprising:
a package substrate;
a first semiconductor chip on the package substrate;
a conductive spacer comprising a conductive material, and adjacent the first semiconductor chip on the package substrate;
a second semiconductor chip on the first semiconductor chip and a first portion of the conductive spacer; and
an electromagnetic interference (EMI) shield around and covering the package substrate, the first semiconductor chip, the second semiconductor chip, and the conductive spacer, and electrically connecting to a second portion of the conductive spacer, such that the conductive spacer provides a ground path for the EMI shield.

17. The semiconductor package of claim 16 , further comprising a molding unit under the EMI shield, the molding unit covering a top portion of the package substrate, the first semiconductor chip, the second semiconductor chip, and the first portion of the conductive spacer, and exposing the second portion of the conductive spacer.

18. The semiconductor package of claim 16 , further comprising a first ground pad at a first side of the package substrate electrically connected to the conductive spacer, a second ground pad on a second side of the package substrate opposite the first side, and a ground via extending through the package substrate between the first ground pad and the second ground pad for electrically connecting the first ground pad and the second ground pad.

19. The semiconductor package of claim 16 , further comprising a connection terminal that is attached to a lower surface of the package substrate and electrically connected to the second ground pad.

20. The semiconductor package of claim 16 , wherein a portion of the conductive spacer overlaps the second semiconductor chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Young-Woo

Classifications

• H10W42/276

  the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title