Semiconductor package

Patent metadata

Field	Value
Publication number	US-9633973-B2
Application number	US-201514613357-A
Country	US
Kind code	B2
Filing date	Feb 3, 2015
Priority date	Dec 20, 2012
Publication date	Apr 25, 2017
Grant date	Apr 25, 2017

Abstract

A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate having a circuit pattern;
a first semiconductor chip arranged on the package substrate, the first semiconductor chip comprising:
a first surface facing the package substrate and a second surface opposite the first surface;
a first integrated circuit; and
a through-silicon via, wherein the through-silicon via is arranged in a central region of the first semiconductor chip and is electrically connected to the circuit pattern; and

a pair of second semiconductor chips spaced apart from each other and disposed on the first semiconductor chip, each second semiconductor chip comprising:
a second integrated circuit;
a third surface facing the first semiconductor chip; and
a fourth surface opposite the third surface,

wherein the first semiconductor chip further comprises first bonding pads disposed on the second surface and connected to the through-silicon via, and
wherein each of the second semiconductor chips further comprises a second bonding pad disposed on the fourth surface and electrically connected to the second integrated circuit.

2. The semiconductor package of claim 1 , wherein the first semiconductor chips have a memory capacity that is two times that of each of the second semiconductor chips, and wherein a total memory capacity of the package is 2n times a memory capacity of the first semiconductor chip, where n is an integer.

3. The semiconductor package of claim 1 , further comprising a first bumper arranged between the first semiconductor chip and the package substrate to electrically connect the through-silicon via to the circuit pattern.

4. The semiconductor package of claim 1 , further comprising:
a pair of third semiconductor chips spaced apart from each other and arranged on the second semiconductor chips, each of the third semiconductor chips comprising:
a third integrated circuit; and
a third bonding pad, wherein the third bonding pad is located near an edge portion of each of the third semiconductor chips, and wherein the third bonding pad is electrically connected to the third integrated circuit; and

a pair of fourth semiconductor chips spaced apart from each other and arranged on the third semiconductor chips, each of the fourth semiconductor chips comprising:
a fourth integrated circuit; and
a fourth bonding pad, wherein the fourth bonding pad is located near an edge portion of each of the fourth semiconductor chips, and wherein the fourth bonding pad is electrically connected to the fourth integrated circuit.

5. The semiconductor package of claim 4 , wherein each of the third semiconductor chips has a fifth surface facing the second semiconductor chips and a sixth surface opposite the fifth surface, and wherein the third bonding pads are disposed on the sixth surfaces, and
wherein each of the fourth semiconductor chips has a seventh surface facing the sixth surface of a corresponding each of the third semiconductor chips and an eighth surface opposite the seventh surface, and wherein the fourth bonding pads are disposed on the eighth surfaces.

6. The semiconductor package of claim 5 , wherein each of the second semiconductor chips further comprises a connection pad on the third surface, and
wherein the semiconductor package further comprises second bumpers disposed between the first and second semiconductor chips to electrically connect the connection pads to the first bonding pads.

7. The semiconductor package of claim 6 , wherein corresponding ones of the connection pads, the second bonding pads, the third bonding pads, and the fourth bonding pads are connected to each other in a side connection manner.

8. The semiconductor package of claim 5 , wherein the third semiconductor chips are shifted toward an edge of the package substrate to expose the second bonding pads of the second semiconductor chips, and
wherein the fourth semiconductor chips are shifted toward the edge of the package substrate to expose the third bonding pads of the third semiconductor chips.

9. The semiconductor package of claim 8 , wherein the second semiconductor chips further comprise connection pads arranged on the third surfaces,
wherein the semiconductor package further comprises second bumpers disposed between the first semiconductor chip and the second semiconductor chips to connect the connection pads to corresponding ones of the first bonding pads, and
wherein corresponding ones of the connection pads, the second bonding pads, the third bonding pads, and the fourth bonding pads are connected to each other in a side connection manner.

10. The semiconductor package of claim 1 , wherein the first bonding pads are also provided on the first surface.

11. The semiconductor package of claim 1 , wherein the first semiconductor chip further comprises first bonding pads provided on the first surface and connected to the through-silicon via, and
wherein each of the second semiconductor chips further comprises a second bonding pad arranged on the third surface and electrically connected to the second integrated circuit.

12. A semiconductor package, comprising:
a package substrate having a circuit pattern;
a first semiconductor chip arranged on the package substrate, the first semiconductor chip comprising:
a first surface facing the package substrate and a second surface opposite the first surface;
a first integrated circuit;
a through-silicon via, wherein the through-silicon via is arranged in a central region of the first semiconductor chip and is electrically connected to the circuit pattern; and
first bonding pads provided on the first surface and connected to the through-silicon via;

a pair of second semiconductor chips spaced apart from each other and disposed on the first semiconductor chip, each second semiconductor chip comprising:
a second integrated circuit;
a third surface facing the first semiconductor chip;
a fourth surface opposite the third surface; and
a second bonding pad arranged on the third surface and electrically connected to the second integrated circuit;

a third semiconductor chip disposed on each of the second semiconductor chips, each of the third semiconductor chip comprising:
a third integrated circuit; and
a third bonding pad, wherein the third bonding pad is located near an edge portion of each of the third semiconductor chips and is electrically connected to the third integrated circuit; and

a fourth semiconductor chip disposed on each of the third semiconductor chips, wherein each of the fourth semiconductor chips comprising:
a fourth integrated circuit; and
a fourth bonding pad, wherein the fourth bonding pad is located near an edge portion of each of the fourth semiconductor chips and is electrically connected to the fourth integrated circuit.

13. The semiconductor package of claim 12 , wherein each of the third semiconductor chips has a fifth surface facing a corresponding second semiconductor chip and a sixth surface opposite the fifth surface, and wherein the third bonding pad is disposed on the fifth surface, and
wherein each of the fourth semiconductor chips has a seventh surface facing the sixth surface of a corresponding third semiconductor chip and an eighth surface opposite the seventh surface, and wherein the fourth bonding pad is disposed on the seventh surface.

14. The semiconductor package of claim 13 , wherein corresponding ones of the second bonding pads, the third bonding pads, and the fourth bonding pads are connected to each other in a side connection manner.

15. The semiconductor package of claim 13 , wherein the third semiconducto

Assignees

• Kim Kilsoo
• Kang Sunwon
• Samsung Electronics Co Ltd

Inventors

• Kim Kilsoo
• Kang Sunwon

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title