Hybrid trigate and nanowire CMOS device architecture

Patent metadata

Field	Value
Publication number	US-10411090-B2
Application number	US-201515745417-A
Country	US
Kind code	B2
Filing date	Sep 24, 2015
Priority date	Sep 24, 2015
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Hybrid trigate and nanowire CMOS device architecture, and methods of fabricating hybrid trigate and nanowire CMOS device architecture, are described. For example, a semiconductor structure includes a semiconductor device of a first conductivity type having a plurality of vertically stacked nanowires disposed above a substrate. The semiconductor structure also includes a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device having a semiconductor fin disposed above the substrate.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a semiconductor device of a first conductivity type, comprising:
a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region;
a common gate electrode stack of the first conductivity type surrounding each of the discrete channel regions of the plurality of vertically stacked nanowires; and
source and drain regions of the first conductivity type on either side of the discrete channel regions of the plurality of vertically stacked nanowires; and

a semiconductor device of a second conductivity type opposite the first conductivity type, the second semiconductor device comprising:
a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces;
a gate electrode stack of the second conductivity type disposed on the top and side surfaces of the channel region of the semiconductor fin; and
source and drain regions of the second conductivity type on either side of the channel region of the semiconductor fin.

2. The semiconductor structure of claim 1 , wherein the plurality of vertically stacked nanowires is a plurality of vertically stacked nanowires of a first semiconductor material, and wherein the semiconductor fin is a semiconductor fin of a second semiconductor material different from the first semiconductor material.

3. The semiconductor structure of claim 2 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.

4. The semiconductor structure of claim 1 , wherein the plurality of vertically stacked nanowires is a plurality of vertically stacked silicon nanowires.

5. The semiconductor structure of claim 1 , wherein the semiconductor fin is a silicon germanium semiconductor fin.

6. The semiconductor structure of claim 5 , wherein the semiconductor fin is an essentially homogeneous silicon germanium semiconductor fin.

7. The semiconductor structure of claim 5 , wherein the semiconductor fin is a precisely homogeneous silicon germanium semiconductor fin.

8. The semiconductor structure of claim 1 , wherein the source and drain regions of the first conductivity type are a pair source and drain region common to all of the discrete channel regions of the plurality of vertically stacked nanowires.

9. The semiconductor structure of claim 1 , wherein the source and drain regions of the first conductivity type are a plurality of discrete source and drain region pairs each corresponding to a discrete channel region of one of the nanowires.

10. The semiconductor structure of claim 1 , further comprising:
a first pair of dielectric spacers on either side of the common gate electrode stack of the first conductivity type; and
a second pair of dielectric spacers on either side of the gate electrode stack of the second conductivity type.

11. The semiconductor structure of claim 1 , wherein the common gate electrode stack of the first conductivity type comprises a first high-k gate dielectric layer disposed on and surrounding each of the discrete channel regions of the plurality of vertically stacked silicon nanowires, and the gate electrode stack of the second conductivity type comprises a second high-k gate dielectric layer disposed on the top and side surfaces of the channel region of the semiconductor fin.

12. The semiconductor structure of claim 11 , wherein the common gate electrode stack of the first conductivity type further comprises a first metal gate disposed on the first high-k gate dielectric layer, and the gate electrode stack of the second conductivity type further comprises a second metal gate disposed on the second high-k gate dielectric layer.

13. The semiconductor device of claim 1 , wherein the semiconductor device of the first conductivity type is an NMOS semiconductor device, and the semiconductor device of the second conductivity type is a PMOS semiconductor device.

Assignees

• Intel Corp

Inventors

• Weber Cory E
• Mehandru Rishabh
• Cea Stephen M

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H01L21/324

  Electricity · mapped topic

• H01L21/02236

  Electricity · mapped topic