Non-Planar Semiconductor Device Having Hybrid Geometry-Based Active Region

Patent metadata

Field	Value
Publication number	US-2016276484-A1
Application number	US-201315024714-A
Country	US
Kind code	A1
Filing date	Dec 19, 2013
Priority date	Dec 19, 2013
Publication date	Sep 22, 2016
Grant date	—

Abstract

Non-planar semiconductor devices having hybrid geometry-based active regions are described. For example, a semiconductor device includes a hybrid channel region including a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion. A gate stack is disposed on exposed surfaces of the hybrid channel region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. Source and drain regions are disposed on either side of the hybrid channel region.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a hybrid channel region comprising a nanowire portion disposed above an omega-FET portion disposed above a fin-FET portion; a gate stack disposed on exposed surfaces of the hybrid channel region, the gate stack comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; and source and drain regions disposed on either side of the hybrid channel region.

2 . The semiconductor device of claim 1 , wherein the nanowire portion and the fin-FET portion of the hybrid channel region consist essentially of a first semiconductor material, and wherein the omega-FET portion comprises a bi-layer comprising an upper layer consisting essentially of the first semiconductor material and a lower layer consisting essentially of a second, different, semiconductor material.

3 . The semiconductor device of claim 2 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.

4 . The semiconductor device of claim 2 , wherein the lower layer of the omega-FET portion of the hybrid channel region is disposed on the fin-FET portion of the hybrid channel region.

5 . The semiconductor device of claim 1 , wherein the fin-FET portion of the hybrid channel region is continuous with a bulk semiconductor substrate.

6 . The semiconductor device of claim 5 , wherein the gate stack is isolated from the bulk semiconductor substrate by a shallow trench isolation (STI) region or a bottom gate isolation (BGI) structure.

7 . A semiconductor device, comprising:
a hybrid channel region comprising a first region disposed above a second region disposed above and spaced apart from a third region, and comprising a fourth region disposed between and in contact with the first and second regions, wherein the first region, the second region and the third region consist essentially of a first semiconductor material, and wherein the fourth region consists essentially of a second, different, semiconductor material; a gate stack disposed on exposed surfaces of the hybrid channel region, the gate stack comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; and source and drain regions disposed on either side of the hybrid channel region.

8 . The semiconductor device of claim 7 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.

9 . The semiconductor device of claim 7 , wherein the hybrid channel region has a length between the source and drain regions, and wherein the fourth semiconductor region is shorter than each of the first, second, and third semiconductor regions in a direction perpendicular to the length of the channel region.

10 . The semiconductor device of claim 7 , wherein the third region of the hybrid channel region is continuous with a bulk semiconductor substrate.

11 . The semiconductor device of claim 10 , wherein the gate stack is isolated from the bulk semiconductor substrate by a shallow trench isolation (STI) region or a bottom gate isolation (BGI) structure.

12 . A semiconductor device, comprising:
a hybrid channel region comprising a first region disposed above and spaced apart from a second region disposed above a third region, and comprising a fourth region disposed between and in contact with the second and third regions, wherein the first region, the second region and the third region consist essentially of a first semiconductor material, and wherein the fourth region consists essentially of a second, different, semiconductor material; a gate stack disposed on exposed surfaces of the hybrid channel region, the gate stack comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer; and source and drain regions disposed on either side of the hybrid channel region.

13 . The semiconductor device of claim 12 , wherein the first semiconductor material is silicon, and the second semiconductor material is silicon germanium.

14 . The semiconductor device of claim 12 , wherein the hybrid channel region has a length between the source and drain regions, and wherein the fourth semiconductor region is shorter than each of the first, second, and third semiconductor regions in a direction perpendicular to the length of the channel region.

15 . The semiconductor device of claim 12 , wherein the third region of the hybrid channel region is continuous with a bulk semiconductor substrate.

16 . The semiconductor device of claim 15 , wherein the gate stack is isolated from the bulk semiconductor substrate by a shallow trench isolation (STI) region or a bottom gate isolation (BGI) structure.

17 . A method of fabricating a hybrid geometry-based semiconductor structure, the method comprising:
forming an epitaxial material stack above a semiconductor substrate, the epitaxial material stack comprising a first layer formed above a second layer formed above a third layer formed above a fourth layer formed on the semiconductor substrate, wherein the first layer, the third layer and the semiconductor substrate consist essentially of a first semiconductor material, wherein the second layer consists essentially of a second semiconductor material different than the first semiconductor material, and wherein the fourth layer consists essentially of a third semiconductor material different than the first and second semiconductor materials; patterning the epitaxial material stack and a portion of the semiconductor substrate to form a semiconductor fin; exposing the semiconductor fin to an etchant to completely remove one of the second and third semiconductor materials and to only partially remove the other of the second and third semiconductor materials selective to the first semiconductor material; and, subsequently, forming a gate electrode stack on the semiconductor fin, with source and drain regions on either side of the gate electrode stack.

18 . The method of claim 17 , wherein exposing the semiconductor fin to the etchant comprises completely removing the second layer of the epitaxial material stack, and wherein the first semiconductor material is silicon, the second semiconductor material is Si y Ge 1-y , and the third semiconductor material is Si x Ge 1-x , where x>y.

19 . The method of claim 17 , wherein exposing the semiconductor fin to the etchant comprises completely removing the fourth layer of the epitaxial material stack, and wherein the first semiconductor material is silicon, the third semiconductor material is Si y Ge 1-y , and the second semiconductor material is Si x Ge 1-x , where x>y.

20 . The method of claim 17 , wherein exposing the semiconductor fin to the etchant comprises wet etching with a composition selected from the group consisting of an aqueous carboxylic acid/nitric acid/HF solution and an aqueous citric acid/nitric acid/HF solution.

21 . The method of claim 17 , wherein forming the gate electrode stack comprises using a replacement gate process.

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Rios Rafael
• Ferdousi Fahmida
• Kuhn Kelin J

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title