Backside fin recess control with multi-hsi option

Patent metadata

Field	Value
Publication number	US-10600810-B2
Application number	US-201515752241-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

Embodiments of the present invention are directed to formation of fins with different active channel heights in a tri-gate or a Fin-FET device. In an embodiment, at least two fins are formed on a front side of the substrate. A gate structure extends over a top surface and a pair of sidewalls of at least a portion of the fins. In an embodiment, the substrate is thinned to expose the bottom surface of the fins. Next, backside etching may be performed on each fin to form active channel regions. The fins may be recessed to different depths, forming active channel regions with differing heights.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first fin comprising:
a first active channel region on a top portion of the first fin;
a first sub-channel region underneath the first active channel region; and
a first active channel height from a top surface of the first active channel region to a top surface of the first sub-channel region; and

a second fin comprising:
a second active channel region on a top portion of the second fin;
a second sub-channel region underneath the second active channel region of the second fin, wherein the first and second sub-channel regions comprise an insulator material;
a second active channel height from a top surface of the second active channel region to a top surface of the second sub-channel region,

wherein the first and second fins have a same height and the first active channel height is substantially different from the second active channel height; and
etch stop layers between the active channel regions and the sub-channel regions, wherein first surfaces of the etch stop layers are in contact with the active channel region and second surfaces of the etch stop layers are in contact with the insulator material of the first and second sub-channel regions.

2. The semiconductor of claim 1 , wherein the etch stop layers include epitaxial material.

3. The semiconductor of claim 1 , wherein the etch stop layers include ion impurities.

4. The semiconductor of claim 3 , wherein the ion impurities comprise a material selected from the group consisting of phosphorous (P), arsenic (As), antimony (Sb), and boron (B).

5. The semiconductor device of claim 1 , wherein the first active channel region includes an etch stop layer.

6. The semiconductor device of claim 1 , wherein the sub-channel regions comprise an air-gap.

7. The semiconductor device of claim 1 , wherein the sub-channel regions comprise oxide material.

Assignees

• Intel Corp

Inventors

• Lilak Aaron D
• Morrow Patrick
• Cea Stephen M
• Mehandru Rishabh
• Weber Cory E

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/40

  into insulating materials · CPC title

• H10P30/21

  of electrically active species · CPC title