Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance

Patent metadata

Field	Value
Publication number	US-11515427-B2
Application number	US-202016901852-A
Country	US
Kind code	B2
Filing date	Jun 15, 2020
Priority date	Jun 15, 2020
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

First claim

What is claimed is:

1. A method comprising:
epitaxially growing a plurality of first lower source-drain regions within a substrate, the plurality of first lower source-drain regions being doped with one of an n-type dopant and a p-type dopant, portions of the substrate laterally adjacent the plurality of first lower source-drain regions being doped with an opposite one of the n-type dopant and the p-type dopant to form a plurality of second lower source-drain regions;
forming an undoped silicon layer over the substrate with the plurality of first lower source-drain regions and the plurality of second lower source-drain regions;
etching the undoped silicon layer to form fins with outer surfaces, the etching extending completely through the undoped silicon layer into the plurality of first lower source-drain regions and the plurality of second lower source-drain regions, the etching defining bottom junctions beneath the fins, the fins and the bottom junctions defining intermediate cavities;
forming lower spacers, gates, and upper spacers in the intermediate cavities;
forming top junctions on the outer surfaces of the fins;
forming doped epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the plurality of first lower source-drain regions, the doped epitaxially grown first upper source-drain regions being doped with the one of an n-type dopant and a p-type dopant; and
forming second upper source-drain regions outward of the upper spacers and opposite the plurality of second lower source-drain regions, the second upper source-drain regions being doped with the opposite one of the n-type dopant and the p-type dopant.

2. The method of claim 1 , wherein:
the forming of the top junctions on the outer surfaces of the fins comprises forming a first plurality of the top junctions outward of the plurality of first lower source-drain regions and a second plurality of the top junctions outward of the plurality of second lower source-drain regions;
the forming of the doped epitaxially grown first upper source-drain regions comprises forming the doped epitaxially grown first upper source-drain regions in contact with the first plurality of the top junctions; and
the forming of the second upper source-drain regions comprises forming the second upper source-drain regions in contact with the second plurality of the top junctions.

3. The method of claim 2 , wherein the etching comprises reactive ion etching and extends into the plurality of first lower source-drain regions and the plurality of second lower source-drain regions by a dimension RIE, and wherein forming the lower spacers comprises depositing dielectric material to a depth t s , such that a lower junction-channel proximity x is given by x=t s −RIE.

4. The method of claim 3 , wherein, in the etching step, the dimension RIE ranges from about 6 nm to about 10 nm.

5. The method of claim 3 , wherein in depositing the dielectric material to the depth t s , said depth t s ranges from about 5 nm to about 20 nm.

6. The method of claim 3 , wherein in depositing the dielectric material to the depth t s , said depth t s ranges from about 5 nm to about 15 nm.

7. The method of claim 3 , wherein in depositing the dielectric material to the depth t s , said depth t s ranges from about 5 nm to about 12 nm.

8. The method of claim 3 , wherein in depositing the dielectric material to the depth t s , said depth t s ranges from about 9 nm to about 12 nm.

9. The method of claim 3 , wherein the lower junction-channel proximity x ranges from about −3 nm to about 10 nm.

10. The method of claim 3 , wherein:
the one of an n-type dopant and a p-type dopant comprises the p-type dopant; and
the opposite one of the n-type dopant and the p-type dopant comprises the n-type dopant.

11. A method comprising:
encoding, into a design structure embodied on a non-transitory computer-readable medium, a design for an integrated circuit, the design structure specifying:
a substrate having a plurality of first lower source-drain regions and a plurality of second lower source-drain regions, the plurality of first lower source-drain regions being doped with one of an n-type dopant and a p-type dopant, the plurality of second lower source drain regions being doped with an opposite one of the n-type dopant and the p-type dopant, the plurality of first lower source drain regions and the plurality of second lower source drain regions having coplanar outer surfaces;
a first plurality of bottom junctions extending from the outer surfaces of the plurality of first lower source-drain regions;
a second plurality of bottom junctions extending from the outer surfaces of the plurality of second lower source-drain regions;
a first plurality of fins located on the first plurality of bottom junctions, the first plurality of fins having outer ends;
a second plurality of fins located on the second plurality of bottom junctions, and, cooperatively with the first plurality of fins, defining intermediate cavities, the second plurality of fins having outer ends, the intermediate cavities extending into the plurality of first lower source drain regions and the plurality of second lower source-drain regions;
a plurality of spacer-gate structures located in the intermediate cavities, the plurality of spacer-gate structures including lower spacers of dielectric material having a depth t s , and the first and second pluralities of bottom junctions extending outward from the plurality of first lower source drain regions and the plurality of second lower source-drain regions by a distance RIE, such that a lower junction-channel proximity x is given by x=t s −RIE, the plurality of spacer-gate structures further including: gates outward of the lower spacers, and upper spacers outward of the gates, the lower junction-channel proximity being defined between outer surfaces of the bottom junctions and inner edges of the gates;
a first plurality of top junctions located on the outer ends of the first plurality of fins;
a second plurality of top junctions located on the outer ends of the second plurality of fins;
a plurality of first upper source-drain regions located outwardly of the plurality of spacer-gate structures in contact with the first plurality of top junctions, the plurality of first upper source-drain regions being doped with the one of an n-type dopant and a p-type dopant; and
a plurality of second upper source-drain regions located outwardly of the plurality of spacer-gate structures in contact with the second plurality of top junctions, the plurality of second upper source-drain regions being doped with the opposite one of the n-type dopant and the p-type dopant; and

cooperatively specifying, within the design structure, the spacer thickness t s and the distance RIE, such that the lower junction-channel proximity results in adequate performance with parasitic capacitance less than a predetermined value and dielectric breakdown greater than a predetermined value.

12. The method of claim 11 , further comprising providing the design structure to a foundry over a network.

13. The method of claim 11 , further comprising fabricating an integrated circuit in accordance with the design structure.

Assignees

• IBM

Inventors

• Zhao Kai
• Siddiqui Shahab
• Dechene Daniel James
• Krishnan Rishikesh
• Adams Charlotte Dewan

Classifications

• H01L29/66666

  Electricity · mapped topic

• H01L29/78642 Primary

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic