Buried contact structures for a vertical field-effect transistor

Patent metadata

Field	Value
Publication number	US-9831317-B1
Application number	US-201715447639-A
Country	US
Kind code	B1
Filing date	Mar 2, 2017
Priority date	Mar 2, 2017
Publication date	Nov 28, 2017
Grant date	Nov 28, 2017

Abstract

Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

First claim

What is claimed is:

1. A structure comprising:
a first vertical field-effect transistor having a source/drain region located in a first section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the first section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin of the first vertical field-effect transistor; and
a first contact located in a first trench defined in the first section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin of the first vertical field-effect transistor, the first contact coupled with the source/drain region of the first vertical field-effect transistor.

2. The structure of claim 1 further comprising:
a second vertical field-effect transistor having a source/drain region located in a second section of the semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the second section of the semiconductor layer and coupled with the first semiconductor fin and the second semiconductor fin of the second vertical field-effect transistor; and
a second contact located in a second trench defined in the second section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin of the second vertical field-effect transistor, the second contact coupled with the source/drain region of the second vertical field-effect transistor.

3. The structure of claim 2 wherein the first contact is coupled with the second contact such that the source/drain region of the first vertical field-effect transistor is coupled with the source/drain region of the second vertical field-effect transistor.

4. The structure of claim 3 further comprising:
a third contact in a third trench partially located in the first section of the semiconductor layer and partially located in the second section of the semiconductor layer, the third contact directly coupling the first contact with the second contact.

5. The structure of claim 4 wherein the third contact is located between the first semiconductor fin and the second semiconductor fin of the first vertical field-effect transistor and the first semiconductor fin and the second semiconductor fin of the second vertical field-effect transistor.

6. The structure of claim 5 wherein the first contact is aligned parallel to the first semiconductor fin and the second semiconductor fin of the first vertical field-effect transistor, the second contact is aligned parallel to the first semiconductor fin and the second semiconductor fin of the second vertical field-effect transistor, and the third contact is aligned perpendicular to the first contact and the second contact.

7. The structure of claim 3 further comprising:
a first middle-of-line contact extending vertically to contact either the source/drain region of the first vertical field-effect transistor or the source/drain region of the second vertical field-effect transistor,
wherein the other of the source/drain region of the first vertical field-effect transistor or the source/drain region of the second vertical field-effect transistor is not contacted by a second middle-of-line contact.

8. The structure of claim 2 wherein the first section of the semiconductor layer is located in a first well, the second section of the semiconductor layer is located in a second well of opposite conductivity type from the first well, and the first well intersects the second well along a vertical junction located between the first section of the semiconductor layer and the second section of the semiconductor layer.

9. The structure of claim 2 further comprising:
a trench isolation region surrounding the first section of the semiconductor layer and the second section of the semiconductor layer,
wherein the trench isolation region is absent between the first semiconductor fin and the second semiconductor fin of the first vertical field-effect transistor and between the first semiconductor fin and the second semiconductor fin of the second vertical field-effect transistor.

10. The structure of claim 2 wherein the first section of the semiconductor layer and the second section of the semiconductor layer are located vertically above a first doped layer, a second doped layer, and a substrate with the second doped layer vertically between the first doped layer and the substrate, and the second doped layer has an opposite conductivity type from the first doped layer and the substrate.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Lee Tek Po Rinus

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H01L29/66666

  Electricity · mapped topic

• H01L29/41741 Primary

  Electricity · mapped topic