Techniques for enhancing vertical gate-all-around FET performance

Patent metadata

Field	Value
Publication number	US-10453844-B2
Application number	US-201715833543-A
Country	US
Kind code	B2
Filing date	Dec 6, 2017
Priority date	Dec 6, 2017
Publication date	Oct 22, 2019
Grant date	Oct 22, 2019

Abstract

Techniques for enhancing VFET performance are provided. In one aspect, a method of forming a VFET device includes: patterning a fin(s) in a substrate; forming bottom source and drains at a base of the fin(s); forming bottom spacers on the bottom source and drains; forming a gate along sidewalls of the fin(s); recessing the gate to expose a top portion of the fin(s); forming an oxide layer along the sidewalls of the top portion of the fin(s); depositing a charged layer over the fin(s) in contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the fin(s) forming a dipole; forming top spacers above the gate; and forming top source and drains above the top spacers. A method of forming a VFET device having both NFETs and PFETs is also provided as are VFET devices formed by the present techniques.

First claim

What is claimed is:

1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:
patterning at least one fin in a substrate;
forming bottom source and drains at a base of the at least one fin;
forming bottom spacers on the bottom source and drains;
forming a gate along sidewalls of the at least one fin;
recessing the gate to expose a top portion of the at least one fin;
forming a native oxide layer along the sidewalls of the top portion of the at least one fin;
depositing a charged layer over the at least one fin in direct contact with the native oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole;
forming top spacers above the gate; and
forming top source and drains above the top spacers.

2. The method of claim 1 , wherein the charged layer has a positive charge.

3. The method of claim 2 , wherein the charged layer is formed from a material selected from the group consisting of: strontium oxide (SrO), lanthanum oxide (La 2 O 3 ), lutetium oxide (Lu 2 O 3 ), yttrium oxide (Y 2 O 3 ), and combinations thereof.

4. The method of claim 1 , wherein the charged layer has a negative charge.

5. The method of claim 4 , wherein the charged layer is formed from a material selected from the group consisting of: aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), magnesium oxide (MgO), and combinations thereof.

6. The method of claim 1 , wherein the step of forming the gate comprises the step of:
depositing a conformal gate dielectric over the at least one fin; and
depositing a conformal gate conductor over the conformal gate dielectric.

7. The method of claim 6 , wherein the conformal gate dielectric comprises a high-κ material selected from the group consisting of: hafnium oxide (HfO 2 ), lanthanum oxide (La 2 O 3 ), and combinations thereof.

8. The method of claim 6 , wherein conformal gate conductor comprises a workfunction setting metal selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), aluminum (Al)-containing alloys, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), titanium aluminum carbide (TiAlC), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tungsten (W), and combinations thereof.

Assignees

• IBM

Inventors

• Ok Injo
• Lee Choonghyun
• Seo Soon-Cheon
• Kim Seyoung

Classifications

• H01L29/7827

  Electricity · mapped topic

• H01L21/823885

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic

• H01L21/823821

  Electricity · mapped topic

• H01L29/51

  Electricity · mapped topic