Self-aligned source/drain junction for vertical field-effect transistor (FET) and method of forming the same

Patent metadata

Field	Value
Publication number	US-9761728-B1
Application number	US-201615164253-A
Country	US
Kind code	B1
Filing date	May 25, 2016
Priority date	May 25, 2016
Publication date	Sep 12, 2017
Grant date	Sep 12, 2017

Abstract

A method for manufacturing a semiconductor device includes forming a bottom source/drain region on a substrate, forming a semiconductor layer on the bottom source/drain region, patterning the semiconductor layer into a plurality of channel regions extending vertically with respect to the substrate, conformally forming a lower dielectric layer on the patterned semiconductor layer, forming a lower spacer layer on a portion of the lower dielectric layer, removing an exposed portion of the lower dielectric layer, forming a gate structure around the plurality of channel regions and on the lower spacer layer, and doping portions of the plurality of channel regions corresponding to the lower spacer layer, wherein the doping comprises diffusing a dopant from the lower dielectric layer into the portions of the plurality of channel regions.

First claim

We claim:

1. A method for manufacturing a semiconductor device, comprising:
forming a bottom source/drain region on a substrate;
forming a semiconductor layer on the bottom source/drain region;
patterning the semiconductor layer into a plurality of channel regions extending vertically with respect to the substrate;
conformally forming a lower dielectric layer on the patterned semiconductor layer;
forming a lower spacer layer on a portion of the lower dielectric layer;
removing an exposed portion of the lower dielectric layer;
forming a gate structure around the plurality of channel regions and on the lower spacer layer; and
doping portions of the plurality of channel regions corresponding to the lower spacer layer, wherein the doping comprises diffusing a dopant from the lower dielectric layer into the portions of the plurality of channel regions.

2. The method according to claim 1 , wherein the lower dielectric layer comprises at least one of PSG (phospho-silicate glass), BSG (boro-silicate glass) and BPSG (boro-phospho-silicate glass).

3. The method according to claim 1 , wherein the patterning removes a portion of the semiconductor layer to form the plurality of channel regions, and wherein an unremoved portion of the semiconductor layer remains between the plurality of channel regions and the bottom source/drain region.

4. The method according to claim 3 , wherein a height of the unremoved portion with respect to the bottom source/drain region is about 5 nm to about 10 nm.

5. The method according to claim 3 , wherein the lower dielectric layer is formed on the unremoved portion of the semiconductor layer.

6. The method according to claim 1 , further comprising:
recessing the gate structure; and
conformally forming an upper dielectric layer on the plurality of channel regions and on the recessed gate structure.

7. The method according to claim 6 , further comprising forming an upper spacer layer on a portion of the upper dielectric layer.

8. The method according to claim 7 , further comprising doping portions of the plurality of channel regions corresponding to the upper spacer layer, wherein the doping comprises diffusing a dopant from the upper dielectric layer into the portions of the plurality of channel regions corresponding to the upper spacer layer.

9. The method according to claim 8 , wherein the upper dielectric layer comprises at least one of PSG (phospho-silicate glass), BSG (boro-silicate glass) and BPSG (boro-phospho-silicate glass).

10. The method according to claim 7 , further comprising forming a top source/drain region on the upper spacer layer and the plurality of channel regions.

11. A semiconductor device, comprising:
a substrate;
a bottom source/drain region on a substrate;
a plurality of channel regions extending vertically with respect to the substrate;
a semiconductor layer between the plurality of channel regions and the bottom source/drain region;
a lower dielectric layer on the semiconductor layer and on lower side surfaces of the plurality of channel regions;
a lower spacer layer on the lower dielectric layer; and
a gate structure around the plurality of channel regions and on the lower spacer layer;
wherein portions of the plurality of channel regions corresponding to the lower spacer layer are doped with a dopant from the lower dielectric layer.

12. The semiconductor device according to claim 11 , wherein the lower dielectric layer comprises at least one of PSG (phospho-silicate glass), BSG (boro-silicate glass) and BPSG (boro-phospho-silicate glass).

13. The semiconductor device according to claim 11 , wherein a height of the semiconductor layer with respect to the bottom source/drain region is about 5 nm to about 10 nm.

14. The semiconductor device according to claim 11 , further comprising:
an upper dielectric layer on the gate structure and on upper side surfaces of the plurality of channel regions; and
an upper spacer layer on the upper dielectric layer.

15. The semiconductor device according to claim 14 , wherein portions of the plurality of channel regions corresponding to the upper spacer layer are doped with a dopant from the upper dielectric layer.

16. The semiconductor device according to claim 15 , wherein the upper dielectric layer comprises at least one of PSG (phospho-silicate glass), BSG (boro-silicate glass) and BPSG (boro-phospho-silicate glass).

17. The semiconductor device according to claim 14 , further comprising a top source/drain region on the upper spacer layer and the plurality of channel regions.

18. A method for manufacturing a semiconductor device, comprising:
forming a bottom source/drain region on a substrate;
forming a semiconductor layer on the bottom source/drain region;
patterning the semiconductor layer into a plurality of fins extending vertically with respect to the substrate, wherein the patterning removes a portion of the semiconductor layer to form the plurality of fins, and an unremoved portion of the semiconductor layer remains between the plurality of fins and the bottom source/drain region;
conformally forming a lower dielectric layer on the plurality of fins and on the unremoved portion of the semiconductor layer;
forming a lower spacer layer on a portion of the lower dielectric layer;
removing an exposed portion of the lower dielectric layer;
forming a gate structure around the plurality of fins and on the lower spacer layer; and
doping portions of the plurality of fins corresponding to the lower spacer layer, wherein the doping comprises diffusing a dopant from the lower dielectric layer into the portions of the plurality of channel fins.

19. The method according to claim 18 , wherein the lower dielectric layer comprises at least one of PSG (phospho-silicate glass), BSG (boro-silicate glass) and BPSG (boro-phospho-silicate glass).

20. The method according to claim 19 , further comprising:
recessing the gate structure;
conformally forming an upper dielectric layer on the plurality of fins and on the recessed gate structure; and
forming an upper spacer layer on a portion of the upper dielectric layer.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Miao Xin
• Xu Wenyu
• Zhang Chen

Classifications

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/014

  of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors · CPC title

• H10D62/85

  being Group III-V materials, e.g. GaAs · CPC title

• H01L29/78696

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic