Method for fabricating a semiconductor package

Patent metadata

Field	Value
Publication number	US-11515260-B2
Application number	US-202016874284-A
Country	US
Kind code	B2
Filing date	May 14, 2020
Priority date	Aug 14, 2019
Publication date	Nov 29, 2022
Grant date	Nov 29, 2022

Abstract

A method for fabricating a semiconductor package includes forming a release layer on a first carrier substrate. An etch stop layer is formed on the release layer. A first redistribution layer is formed on the etch stop layer and includes a plurality of first wires and a first insulation layer surrounding the plurality of first wires. A first semiconductor chip is formed on the first redistribution layer. A solder ball is formed between the first redistribution layer and the first semiconductor chip. A second carrier substrate is formed on the first semiconductor chip. The first carrier substrate, the release layer, and the etch stop layer are removed. The second carrier substrate is removed.

First claim

What is claimed is:

1. A method for fabricating a semiconductor package, the method comprising:
forming a release layer on a first carrier substrate;
forming an etch stop layer on the release layer;
forming a first redistribution layer directly on the etch stop layer, the first redistribution layer comprising a plurality of first wires and a first insulation layer surrounding the plurality of first wires;
forming a first semiconductor chip on the first redistribution layer after forming the first redistribution layer;
forming a solder ball between the first redistribution layer and the first semiconductor chip;
forming a second carrier substrate on the first semiconductor chip;
removing the first carrier substrate, the release layer, and the etch stop layer; and
removing the second carrier substrate.

2. The method of claim 1 , wherein:
the release layer has a first etch selectivity;
the etch stop layer has a second etch selectivity that is smaller than the first etch selectivity; and
the etch stop layer comprises metal.

3. The method of claim 2 , wherein the etch stop layer comprises Ti.

4. The method of claim 1 , further comprising:
forming a metal layer on the etch stop layer, the metal layer comprising a material that is different from a material of the etch stop layer.

5. The method of claim 4 , wherein the metal layer and the plurality of first wires comprise a same material.

6. The method of claim 1 , wherein the release layer and the first insulation layer comprise a same material.

7. The method of claim 1 , wherein a thickness of the etch stop layer is in a range of about 100 nm to about 500 nm.

8. The method of claim 1 , further comprising:
forming a second semiconductor chip on the first semiconductor chip,
wherein the second carrier substrate is formed on the second semiconductor chip.

9. The method of claim 8 , further comprising:
forming a via adjacent to the first semiconductor chip and spaced apart from the first semiconductor chip in a direction of a top surface of the first carrier substrate;
wherein the second semiconductor chip is connected to the via.

10. The method of claim 1 , further comprising:
forming a second redistribution layer on the first semiconductor chip, the second redistribution layer comprising a plurality of second wires and a second insulation layer surrounding the plurality of second wires.

11. The method of claim 10 , further comprising:
forming a second semiconductor chip on the second redistribution layer,
wherein the second carrier substrate is formed on the second semiconductor chip.

12. A method for fabricating a semiconductor package, the method comprising:
forming a release layer on a first carrier substrate;
forming an etch stop layer comprising metal on the release layer;
forming a first redistribution layer directly on the etch stop layer, the first redistribution layer comprising a plurality of first wires and a first insulation layer surrounding the plurality of first wires;
forming a first semiconductor chip on the first redistribution layer after forming the first redistribution layer;
forming a solder ball between the first redistribution layer and the first semiconductor chip;
forming a molding layer that covers the first semiconductor chip; and
removing the first carrier substrate, the release layer, and the etch stop layer,
wherein the release layer and the first insulation layer comprise a same material.

13. The method of claim 12 , wherein the etch stop layer comprises Ti.

14. The method of claim 12 , further comprising:
forming a metal layer on the etch stop layer, the metal layer comprising a material that is different from a material of the etch stop layer.

15. The method of claim 14 , wherein the metal layer and the plurality of first wires comprise a same material.

16. The method of claim 14 , wherein a thickness of the metal layer is in a range of about 50 nm to about 350 nm.

17. The method of claim 12 , further comprising:
forming a second semiconductor chip on the first semiconductor chip.

18. A method for fabricating a semiconductor package, the method comprising:
forming a release layer on a first carrier substrate;
forming an etch stop layer comprising metal on the release layer;
forming a first redistribution layer directly on the etch stop layer, the first redistribution layer comprising a plurality of first wires and a first insulation layer surrounding the plurality of first wires;
forming a first semiconductor chip on the first redistribution layer after forming the first redistribution layer;
forming a solder ball between the first redistribution layer and the first semiconductor chip;
forming a molding layer that covers the first semiconductor chip;
forming a second carrier substrate on the molding layer;
removing the first carrier substrate, the release layer, and the etch stop layer; and
removing the second carrier substrate,
wherein the release layer and the first insulation layer comprise a same material.

19. The method of claim 18 , wherein the etch stop layer comprises Ti.

20. The method of claim 18 , wherein a thickness of the etch stop layer is about 100 nm to about 500 nm.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Da Hye
• Kim Dong Kyu
• Park Jung-Ho

Classifications

• H10P72/7448

  the bond interface between the auxiliary support and the wafer comprising two or more, e.g. multilayer adhesive or adhesive and release layer · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title