Semiconductor device and method

Patent metadata

Field	Value
Publication number	US-9646918-B2
Application number	US-201414460089-A
Country	US
Kind code	B2
Filing date	Aug 14, 2014
Priority date	Aug 14, 2014
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

First claim

What is claimed is:

1. A semiconductor device comprising:
a redistribution layer with a first portion and a second portion;
a first passivation layer on the redistribution layer, the first passivation layer having a first side and a second side opposite the first side;
an encapsulant contacting the first side of the first passivation layer;
a through via in connection with the first portion of the redistribution layer, the through via extending through the encapsulant and away from the first side of the first passivation layer a first distance;
a first dummy portion in connection with the second portion of the redistribution layer, the first dummy portion in physical contact with the encapsulant, the first dummy portion being a conductive material, the first dummy portion extending through the encapsulant and away from the first side of the first passivation layer a second distance, the second distance less than the first distance; and
a first die embedded within the encapsulant.

2. The semiconductor device of claim 1 , further comprising:
a second passivation layer in contact with the second side of the first passivation layer; and
an opening through the second passivation layer and the first passivation layer, wherein the opening exposes the second portion of the redistribution layer.

3. The semiconductor device of claim 2 , further comprising a solder bump within the opening.

4. The semiconductor device of claim 1 , wherein the redistribution layer, the through via, and the first die are part of an integrated fan out package.

5. The semiconductor device of claim 1 , wherein the first dummy portion comprises copper.

6. The semiconductor device of claim 5 , wherein the first dummy portion further comprises a seed layer.

7. The semiconductor device of claim 1 , further comprising a package electrically bonded to the second side of the first passivation layer.

8. A semiconductor device comprising:
a first die;
an encapsulant in contact with and extending away from a sidewall of the first die;
a through via laterally separated from the first die and extending through the encapsulant;
a first redistribution layer over the encapsulant, wherein a first portion of the first redistribution layer is in contact with the through via; and
a conductive dummy portion in contact with a second portion of the first redistribution layer, the conductive dummy portion being located at least partially between the first die and the through via but not extending through the encapsulant, the conductive dummy portion in physical contact with the encapsulant.

9. The semiconductor device of claim 8 , further comprising a second redistribution layer on an opposite side of the encapsulant from the first redistribution layer.

10. The semiconductor device of claim 9 , further comprising a package bonded to the second redistribution layer.

11. The semiconductor device of claim 8 , wherein the conductive dummy portion has a non-planar surface.

12. The semiconductor device of claim 8 , further comprising:
a passivation layer in contact with the first redistribution layer; and
an opening through the passivation layer, wherein the opening exposes the second portion of the first redistribution layer, wherein the opening has a first width that is less than a second width of the first redistribution layer.

13. The semiconductor device of claim 8 , further comprising:
a passivation layer in contact with the first redistribution layer; and
an opening through the passivation layer, wherein the opening exposes the second portion of the first redistribution layer, wherein the opening has a first width that is greater than a second width of the first redistribution layer.

14. A semiconductor device comprising:
a first passivation layer;
a first redistribution layer in the first passivation layer, the first redistribution layer having a first side and a second side facing away from the first side;
a first dummy structure in electrical and physical contact with the first side of the first redistribution layer and extending away from the first side of the first redistribution layer a first distance;
a first via in electrical and physical contact with the first side of the first redistribution layer and extending away from the first side of the first redistribution layer a second distance greater than the first distance;
a first semiconductor die attached to the first passivation layer, wherein the first semiconductor die is laterally separated from the first dummy structure and the first via; and
an encapsulant encapsulating the first dummy structure, the first via, and the first semiconductor die, wherein a surface of the encapsulant is planar with the first via and the first semiconductor die, wherein the encapsulant physically contacts the first dummy structure.

15. The semiconductor device of claim 14 , further comprising a second redistribution layer electrically connecting the first via with the first semiconductor die.

16. The semiconductor device of claim 14 , further comprising:
a second passivation layer on an opposite side of the first passivation layer from the first semiconductor die; and
an opening through the second passivation layer, the opening exposing the second side of the first redistribution layer.

17. The semiconductor device of claim 14 , further comprising a first seed layer located between the first dummy structure and the first side of the first redistribution layer.

18. The semiconductor device of claim 17 , further comprising a second seed layer located between the first seed layer and the first dummy structure.

19. The semiconductor device of claim 18 , wherein the first dummy structure has a concave surface.

20. The semiconductor device of claim 14 , wherein the encapsulant is a single, continuous layer of a same molding compound.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Cheng Li-Hui
• Tsai Po-Hao
• Lin Jing-Cheng

Classifications

• H10W90/291

  characterised by containers, encapsulations, or other housings for the stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/60 Primary

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title