Semiconductor device and method of wafer level package integration

Patent metadata

Field	Value
Publication number	US-9460951-B2
Application number	US-201113172680-A
Country	US
Kind code	B2
Filing date	Jun 29, 2011
Priority date	Dec 3, 2007
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

A method of making a wafer level chip scale package includes providing a temporary substrate, and forming a wafer level interconnect structure over the temporary substrate using wafer level processes. The wafer level processes include forming a first insulating layer in contact with an upper surface of the temporary substrate, and forming a first conductive layer in contact with an upper surface of the first passivation layer. A first semiconductor die is mounted over the wafer level interconnect structure such that an active surface of the first semiconductor die is in electrical contact with the first conductive layer, and a first encapsulant is deposited over the first semiconductor die. A second encapsulant is deposited over the first encapsulant, and the first and second encapsulants are cured simultaneously. The temporary substrate is removed to expose the first passivation layer.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a silicon substrate capable of sustaining temperatures equal to or greater than 200° C.;
forming an interconnect structure over the silicon substrate at temperatures equal to or greater than 200° C. by,
(a) forming a multi-layer under bump metallization (UBM) comprising a wetting layer in contact with a surface of the silicon substrate and an adhesion layer formed over the wetting layer,
(b) forming an insulating layer over the multi-layer UBM and substrate, and
(c) forming a conductive layer over the insulating layer;

disposing a semiconductor die over the interconnect structure;
depositing a first encapsulant over the semiconductor die with the first encapsulant disposed over a surface of the semiconductor die opposite the interconnect structure and between the semiconductor die and interconnect structure;
removing a portion of the first encapsulant to planarize the first encapsulant with the surface of the semiconductor die;
depositing a second encapsulant over semiconductor die and first encapsulant;
removing the silicon substrate from over the wetting layer of the multi-layer UBM and insulating layer after disposing the semiconductor die over the interconnect structure; and
forming a plurality of first conductive bumps contacting the wetting layer of the multi-layer UBM.

2. The method of claim 1 , wherein disposing the semiconductor die over the interconnect structure includes:
forming a plurality of second conductive bumps over the semiconductor die; and
bonding the second conductive bumps of the semiconductor die to the interconnect structure.

3. The method of claim 2 , wherein the second conductive bumps include micro bumps.

4. The method of claim 1 , wherein the conductive layer follows a contour of the insulating layer.

5. The method of claim 1 , wherein forming the multi-layer UBM further includes:
forming a barrier layer over the wetting layer; and
forming the adhesion layer over the barrier layer.

6. A method of making a semiconductor device, comprising:
providing a substrate including a semiconductor material capable of sustaining temperatures equal to or greater than 200° C.;
forming a wafer level interconnect structure over the substrate at temperatures equal to or greater than 200° C. by,
(a) forming a multi-layer under bump metallization (UBM) in contact with a surface of the substrate, and
(b) forming an insulating layer over the multi-layer UBM;

disposing a plurality of semiconductor die over the wafer level interconnect structure after forming the wafer level interconnect structure at temperatures equal to or greater than 200° C.;
depositing a continuous flow of a first encapsulant over a surface of the semiconductor die and across an entire surface of the wafer level interconnect structure and between the semiconductor die and wafer level interconnect structure;
removing the substrate from over a surface of the multi-layer UBM opposite the semiconductor die after disposing the semiconductor die over the wafer level interconnect structure; and
forming a bump material contacting the surface of the multi-layer UBM.

7. The method of claim 6 , wherein depositing the first encapsulant includes injecting the first encapsulant into a chase mold.

8. The method of claim 6 , further including drawing the first encapsulant between the semiconductor die and wafer level interconnect structure with a vacuum assist.

9. The method of claim 6 , further including curing the insulating layer at a temperature greater than or equal to 200° C.

10. A method of making a semiconductor device, comprising:
providing a substrate including an insulating material or semiconductor material and capable of sustaining temperatures equal to or greater than 200° C.;
forming a wafer level interconnect structure over the substrate at temperatures equal to or greater than 200° C. by,
(a) forming a first insulating layer on a surface of the substrate, and
(b) forming a conductive layer over the first insulating layer;

disposing a plurality of semiconductor die over the wafer level interconnect structure after forming the wafer level interconnect structure at temperatures equal to or greater than 200° C.;
depositing a continuous flow of a first encapsulant over the semiconductor die and across an entire surface of the wafer level interconnect structure and between the semiconductor die and wafer level interconnect structure; and
forming a plurality of openings in the first insulating layer over a surface of the conductive layer after depositing the first encapsulant.

11. The method of claim 10 , further including forming a plurality of bumps over the semiconductor die.

12. A method of making a semiconductor device, comprising:
providing a substrate capable of sustaining temperatures equal to or greater than 200° C.;
forming a wafer level interconnect structure on the substrate at temperatures equal to or greater than 200° C. by,
(a) forming an insulating layer on the substrate, and
(b) forming a conductive layer over the insulating layer;

disposing a plurality of semiconductor die over the wafer level interconnect structure after forming the wafer level interconnect structure at temperatures equal to or greater than 200° C.;
depositing a continuous flow of a first encapsulant across an entire surface of the wafer level interconnect structure and between the semiconductor die and wafer level interconnect structure; and
forming an opening in the insulating layer over a surface of the conductive layer.

13. The method of claim 12 , further including injecting the first encapsulant into a mold.

14. The method of claim 12 , further including drawing the first encapsulant across the wafer level interconnect structure with a vacuum assist.

15. The method of claim 12 , further including forming a multi-layer under bump metallization (UBM) over the conductive layer.

16. The method of claim 12 , further including:
removing the substrate; and
forming a second interconnect structure over the conductive layer.

17. The method of claim 12 , further including depositing a second encapsulant over the first encapsulant.

18. The method of claim 1 , further including simultaneously curing the second encapsulant and first encapsulant.

19. The method of claim 6 , further including depositing a second encapsulant over the first encapsulant.

20. The method of claim 6 , wherein forming the multi-layer UBM includes:
forming a wetting layer over the substrate;
forming a barrier layer over the wetting layer; and
forming an adhesion layer over the barrier layer.

21. The method of claim 10 , further including:
forming a multi-layer under bump metallization (UBM) over the surface of the conductive layer; and
depositing a second insulating layer over the first insulating layer and multi-layer UBM.

22. The method of claim 10 , further including:
removing the substrate; and
forming a second interconnect structure over the wafer level interconnect structure opposite the semiconductor die.

23. The method of claim 10 , further including depositing a second encapsulant over the first encapsulant.

24. The method of claim 10 , further including:
forming a second insulating over the first insulating layer opposite the conductive layer; and
forming a plurality of second interconnect structures over the surface of the conductive layer.

Assignees

• Lin Yaojian
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title