Methods for reducing contact depth variation in semiconductor fabrication

Patent metadata

Field	Value
Publication number	US-11495494-B2
Application number	US-201916688071-A
Country	US
Kind code	B2
Filing date	Nov 19, 2019
Priority date	Aug 30, 2017
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

An integrated circuit includes a substrate, an isolation feature disposed over the substrate, a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature, and a dielectric layer disposed over the isolation feature. A top surface of the dielectric layer is at a same level as a top surface of the fin or below a top surface of the fin by less than or equal to 15 nanometers.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
an isolation feature disposed over the substrate;
a fin extending from the substrate alongside the isolation feature such that the fin extends above the isolation feature;
a gate structure disposed over the fin;
a dielectric layer disposed directly above the isolation feature, wherein a topmost surface of the dielectric layer is at a same level as a topmost flat surface of the fin or below the topmost flat surface of the fin by less than or equal to 15 nanometers, wherein the topmost flat surface of the fin is directly under the gate structure;
an etch stop layer disposed between the dielectric layer and the isolation feature; and
a conductive feature directly above the isolation feature and directly contacting the dielectric layer, wherein the etch stop layer directly contacts the dielectric layer.

2. The integrated circuit of claim 1 further comprising other gate structures disposed on the fin and on the isolation feature such that a first trench defined by the gate structure and the other gate structures extends directly over the fin and a second trench defined by the gate structure and the other gate structures extends directly over the isolation feature.

3. The integrated circuit of claim 2 , wherein the dielectric layer is disposed in the second trench.

4. The integrated circuit of claim 3 , wherein the etch stop layer is also disposed between the dielectric layer and the other gate structures in the second trench.

5. The integrated circuit of claim 4 , wherein a topmost surface of the etch stop layer is at a same level as or below the topmost surface of the dielectric layer, wherein the dielectric layer is not disposed over the topmost surface of the etch stop layer.

6. The integrated circuit of claim 1 , wherein the etch stop layer is a first etch stop layer, further comprising a second etch stop layer disposed on the topmost surface of the dielectric layer and on the topmost flat surface of the fin.

7. The integrated circuit of claim 6 , further comprising a first contact feature disposed over the dielectric layer and penetrating through the second etch stop layer and a second contact feature disposed over the fin and penetrating through the second etch stop layer.

8. The integrated circuit of claim 1 , wherein the dielectric layer is a first ILD layer, the integrated circuit further comprising a second ILD layer disposed over the first ILD layer and over the fin.

9. The integrated circuit of claim 8 , wherein the etch stop layer is a first etch stop layer and the gate structure is a first gate structure, further comprising a second gate structure disposed over the isolation feature and a second etch stop layer between the second ILD layer and the second gate structure.

10. An integrated circuit comprising:
a substrate;
a fin extending from the substrate;
an isolation feature over the substrate and adjacent to a lower portion of the fin;
gate structures over the fin and over the isolation feature such that a first trench defined by the gate structures extends directly over the fin and a second trench defined by the gate structures extends directly over the isolation feature;
a first dielectric layer in the second trench;
a second dielectric layer over the first dielectric layer and in the second trench;
an etch stop layer in both the first and second trenches and between the first and the second dielectric layers; and
a conductive feature disposed directly over the first dielectric layer in the second trench and penetrating through the second dielectric layer and the etch stop layer.

11. The integrated circuit of claim 10 , further comprising a third dielectric layer between the first dielectric layer and the isolation feature and between the first dielectric layer and the gate structures.

12. The integrated circuit of claim 10 , wherein the second dielectric layer is also disposed in the first trench and the etch stop layer is also disposed between the second dielectric layer and the fin.

13. The integrated circuit of claim 12 , wherein the conductive feature is in direct contact with the first dielectric layer.

14. The integrated circuit of claim 13 , further comprising another conductive feature disposed directly over the fin and penetrating through the second dielectric layer.

15. The integrated circuit of claim 10 , wherein a top surface of the first dielectric layer is at a same level as a top surface of the fin or below the top surface of the fin by less than or equal to 15 nanometers, wherein the top surface of the fin is directly below one of the gate structures.

16. An integrated circuit comprising:
a substrate;
a fin over the substrate;
an isolation feature over the substrate and adjacent to the fin, wherein the fin extends above the isolation feature;
gate structures over the fin and over the isolation feature, thereby defining a first trench extending directly over the fin and a second trench extending directly over the isolation feature;
a first dielectric layer over the isolation feature and in the second trench;
a first etch stop layer between the first dielectric layer and the isolation feature and between the first dielectric layer and the gate structures, wherein the first etch stop layer directly contacts the first dielectric layer;
a second dielectric layer in the first and the second trenches and over the first dielectric layer and over the fin;
a first contact feature directly over the fin and penetrating through the second dielectric layer;
a second contact feature directly contacting the first dielectric layer; and
a second etch stop layer over the first dielectric layer and in the second trench, wherein the second etch stop layer is also in the first trench.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lee Yun
• Lee Chen-Ming
• Yang Fu-Kai
• Huang Yi-Jyun
• Wang Sheng-Hsiung
• Wang Mei-Yun

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P50/283 Primary

  by chemical means · CPC title

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10W20/096

  by contacting with gases, liquids or plasmas · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title