Semiconductor die containing silicon nitride stress compensating regions and method for making the same

Patent metadata

Field	Value
Publication number	US-11430745-B2
Application number	US-202016806087-A
Country	US
Kind code	B2
Filing date	Mar 2, 2020
Priority date	Mar 2, 2020
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

A method of forming a semiconductor structure includes forming first semiconductor devices over a first substrate, forming a first dielectric material layer over the first semiconductor devices, forming vertical recesses in the first dielectric material layer, such that each of the vertical recesses vertically extends from a topmost surface of the first dielectric material layer toward the first substrate, forming silicon nitride material portions in each of the vertical recesses; and locally irradiating a second subset of the silicon nitride material portions with a laser beam. A first subset of the silicon nitride material portions that is not irradiated with the laser beam includes first silicon nitride material portions that apply tensile stress to respective surrounding material portions, and the second subset of the silicon nitride material portions that is irradiated with the laser beam includes second silicon nitride material portions that apply compressive stress to respective surrounding material portions.

First claim

The invention claimed is:

1. A semiconductor structure comprising a first semiconductor die, wherein the first semiconductor die comprises:
a first substrate;
first semiconductor devices located over the first substrate;
a first dielectric material layer located over the first semiconductor devices;
first silicon nitride material portions embedded within an upper portion of the first dielectric material layer and applying tensile stress to respective surrounding material portions;
second silicon nitride material portions embedded within the upper portion of the first dielectric material layer and applying compressive stress to respective surrounding material portions; and
first bonding pads embedded in the upper portion of the first dielectric material layer;
wherein:
the first silicon nitride material portions comprise strips which laterally extend along a first lengthwise direction;
the second silicon nitride material portions comprise strips which laterally extend along a second lengthwise direction that is different from the first lengthwise direction;
top surfaces of the first silicon nitride material portions and top surfaces of the second silicon nitride material portions are within a horizontal plane that includes a top surface of the first dielectric material layer; and
top surfaces of the first bonding pads are located in the horizontal plane including the top surface of the first dielectric material layer.

2. A semiconductor structure comprising a first semiconductor die and a second semiconductor die, wherein:
the first semiconductor die comprises:
a first substrate;
first semiconductor devices located over the first substrate;
a first dielectric material layer located over the first semiconductor devices;
first silicon nitride material portions embedded within an upper portion of the first dielectric material layer and applying tensile stress to respective surrounding material portions;
second silicon nitride material portions embedded within the upper portion of the first dielectric material layer and applying compressive stress to respective surrounding material portions; and
first bonding pads embedded in the upper portion of the first dielectric material layer;

the second semiconductor die that comprises:
a second substrate;
second semiconductor devices located over the second substrate;
a second dielectric material layer located over the second semiconductor devices; and
second bonding pads embedded in the second dielectric material layer and bonded to a respective one of the first bonding pads;

the first semiconductor die comprises a crater region in which a recessed horizontal surface of the first dielectric material layer is vertically recessed from a horizontal bonding interface between the first bonding pads and the second bonding pads toward the first substrate to provide a cavity; and
the second semiconductor die comprises a mesa portion that protrudes away from the second substrate and at least partly fills the cavity in the crater region.

3. The semiconductor structure of claim 2 , wherein:
the first semiconductor die comprises recessed bonding pads located at the recessed horizontal surface; and
the second semiconductor die comprises raised bonding pads located at a planar surface of the mesa portion and bonded to a respective one of the recessed bonding pads.

4. The semiconductor structure of claim 2 , wherein:
the cavity of the crater region is laterally bounded by four sidewalls;
one of the first silicon nitride material portions is physically exposed at one of the four sidewalls; and
one of the second silicon nitride material portions is physically exposed at another of the four sidewalls.

5. A semiconductor structure comprising a first semiconductor die and a second semiconductor die, wherein:
the first semiconductor die comprises:
a first substrate;
first semiconductor devices located over the first substrate;
a first dielectric material layer located over the first semiconductor devices;
first silicon nitride material portions embedded within an upper portion of the first dielectric material layer and applying tensile stress to respective surrounding material portions;
second silicon nitride material portions embedded within the upper portion of the first dielectric material layer and applying compressive stress to respective surrounding material portions; and
first bonding pads embedded in the upper portion of the first dielectric material layer; and

the second semiconductor die comprises:
a second substrate;
second semiconductor devices located over the second substrate;
a second dielectric material layer located over the second semiconductor devices; and
second bonding pads embedded in the second dielectric material layer and bonded to a respective one of the first bonding pads;

the first semiconductor die comprises a plurality of crater regions in which a respective recessed horizontal surface of the first dielectric material layer is vertically recessed from a horizontal bonding interface between the first bonding pads and the second bonding pads toward the first substrate to provide a plurality of cavities;
the second semiconductor die comprises a mesa portion that protrudes away from the second substrate and at least partly fills one of the plurality of cavities; and
additional semiconductor dies are bonded to the first semiconductor die at a respective one of the recessed horizontal surfaces of the first dielectric material layer located in cavities other than the cavity in the second semiconductor die is present.

6. A semiconductor structure comprising:
a first semiconductor die, wherein the first semiconductor die comprises:
a first substrate;
first semiconductor devices located over the first substrate;
a first dielectric material layer located over the first semiconductor devices;
first silicon nitride material portions embedded within an upper portion of the first dielectric material layer and applying tensile stress to respective surrounding material portions; and
second silicon nitride material portions embedded within the upper portion of the first dielectric material layer and applying compressive stress to respective surrounding material portions; and

a plurality of second semiconductor dies, each comprising a second substrate, second semiconductor devices located over the second substrate, a second dielectric material layer located over the second semiconductor devices, and second bonding pads embedded in the second dielectric material layer;
wherein:
the first semiconductor die further comprises crater regions in each of which a recessed horizontal surface of the first dielectric material layer is vertically recessed to provide a cavity, and recessed first bonding pads located at the recessed horizontal surface;
the plurality of second semiconductor dies are located in the respective crater regions in the first semiconductor die; and
the second bonding pads are bonded to a respective one of the recessed first bonding pads.

7. The semiconductor structure of claim 6 , wherein:
the first silicon nitride portions comprise both first silicon nitride strips and first silicon nitride pillars; and
the second silicon nitride portions comprise both second silicon nitride strips and second silicon nitride pillars.

Assignees

• Sandisk Technologies Llc

Inventors

• Wu Chen
• Rabkin Peter
• Chen Yangyin
• Higashitani Masaaki

Classifications

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W80/312

  characterised by the direct bonding of electrically conductive pads · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W72/941

  Dispositions of bond pads · CPC title