Three dimensional NAND device having nonlinear control gate electrodes and method of making thereof

Patent metadata

Field	Value
Publication number	US-9455267-B2
Application number	US-201414491315-A
Country	US
Kind code	B2
Filing date	Sep 19, 2014
Priority date	Sep 19, 2014
Publication date	Sep 27, 2016
Grant date	Sep 27, 2016

Abstract

A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.

First claim

What is claimed is:

1. A monolithic three dimensional NAND memory device, comprising:
a plurality of control gate electrodes extending in a first direction substantially parallel to a major surface of a substrate in at least one active region, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
an interlevel insulating layer located between the first control gate electrode and the second control gate electrode;
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the major surface of the substrate, such that at least one first portion of each of the plurality of semiconductor channels is located in the first device level, and at least one second portion of each of the plurality of semiconductor channels is located in the second device level;
at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels;
at least one first slit trench extending substantially perpendicular to the major surface of the substrate;
a drain electrode that contacts the first wing portion of the semiconductor channel from above; and
a source electrode that contacts the connecting portion of the semiconductor channel from above;

wherein:
each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region;
the semiconductor channel has J-shaped pipe shape;
a wing portion of the J-shaped pipe shape semiconductor channel extends substantially perpendicular to the major surface of the substrate and a connecting portion of the J-shaped pipe shape semiconductor channel which connects to the wing portion extends substantially parallel to the major surface of the substrate;
the source electrode is located in the first slit trench and has a profile complementary to the nonlinear side wall of the plurality of control gate electrodes;
a length of the source electrode extends substantially parallel to the plurality of control gate electrodes and a height of the source electrode extends substantially perpendicular to the major surface of the substrate;
a dielectric material is located in the first slit trench to insulate the source electrode from the plurality of control gate electrodes;
the drain electrode is electrically connected to a bit line which is located above the semiconductor channel; and
the bit line extends substantially perpendicular to the source electrode and substantially parallel to the major surface of the substrate.

2. The device of claim 1 , wherein the nonlinear side wall comprises a curved portion to offset warpage of the substrate by shifting at least part of a stress imposed on the substrate by the plurality of control gate electrodes from the first direction to a second direction which is perpendicular to the first direction.

3. The device of claim 1 , wherein the nonlinear side wall comprises:
a first side wall portion having a first plane;
a second side wall portion having a second plane different from the first plane; and
a third side wall portion connecting the first side wall portion and the second side wall portion.

4. The device of claim 3 , wherein an angle between the first side wall portion and the third side wall portion is between 0° and 90°.

5. The device of claim 2 , wherein the plurality of control gate electrodes have a uniform or non-uniform width along the second direction in the at least one active region.

6. The device of claim 1 , wherein the at least one first slit trench has a side wall complementary to the nonlinear side wall of the control gate electrodes in the at least one active region.

7. The device of claim 6 , further comprising a second slit trench having a profile complementary to the first slit trench, wherein the plurality of control gate electrodes are located between the first slit trench and the second slit trench.

8. The device of claim 7 , further comprising a straight line axis extending in the first direction substantially parallel to the major surface of the substrate, wherein the axis is completely contained within a width of one control gate electrode of the plurality of control gate electrodes in the at least one active region.

9. The device of claim 7 , further comprising a straight line axis extending in the first direction substantially parallel to the major surface of the substrate along a middle of a width of one control gate electrode of the plurality of control gate electrodes, wherein the axis is partially contained within the width of one control gate electrode of the plurality of control gate electrodes, and the axis is partially contained outside the width of the one control gate electrode of the plurality of control gate electrodes in the at least one active region.

10. The device of claim 7 , further comprising:
a p-well in or over the substrate; and
at least one p-well contact having a major axis extending substantially perpendicular to the major surface of the substrate to the p-well;
wherein at least one first portion of the p-well contact is located in a plane containing the first device level, and at least one second portion of the p-well contact is located in a plane containing the second device level.

11. The device of claim 10 , wherein:
the first control gate electrode comprises a first finger portion of a first comb shaped word line located in the first device level;
the first comb shaped word line further comprises a second finger portion and a connecting portion;
the second finger portion of the first comb shaped word line extends in the first direction in the first device level and is separated from the first finger portion by the first slit trench;
the connecting portion of the first comb shaped word line is located outside the at least one active region and connects the first and the second finger portions of the first comb shaped word line to driver circuit contacts;
the second control gate electrode comprises a first finger portion of a second comb shaped word line located in the second device level;
the second comb shaped word line further comprises a second finger portion and a connecting portion;
the second finger portion of the second comb shaped word line extends in the first direction in the second device level and is separated from the first finger portion by the first slit trench; and
the connecting portion of the second comb shaped word line is located outside the at least one active region and connects the first and the second finger portions of the second comb shaped word line to driver circuit contacts.

12. The device of claim 11 , further comprising at least one first dummy word line finger located in the first device level between the second slit trench and a third slit trench, and at least one second dummy word line finger located in the second device level between the second slit trench and the third slit trench.

13. The device of claim 12 , wherein at least one p-well contact region comprises a plurality of pillar shaped p-well contacts which extend through the first and the second dummy word line fingers in a region between a curved portion of the second slit trench and a straight portion of the third slit trench.

14. The device of claim 13 , wherein a first protruding portion of the nonlin

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Zhang Yanli
• Alsmeier Johann

Classifications

• H10P50/264

  by chemical means · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10W20/43

  Layouts of interconnections · CPC title