Memory device containing stress-tunable control gate electrodes

Patent metadata

Field	Value
Publication number	US-9698223-B2
Application number	US-201414553149-A
Country	US
Kind code	B2
Filing date	Nov 25, 2014
Priority date	Nov 25, 2014
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile-stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress-generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material.

First claim

What is claimed is:

1. A three-dimensional memory device comprising:
a stack of alternating layers comprising insulator layers and electrically conductive layers and located over a top surface of a substrate;
a semiconductor channel, wherein at least one end portion of the semiconductor channel extends substantially perpendicular to the top surface of the substrate; and
a memory film located adjacent to the semiconductor channel;

wherein:
each of the electrically conductive layers comprises a first conductive material portion including a tensile-stress-generating metallic material and a second conductive material portion including a compressive-stress-generating metallic material;
the first conductive material portion comprises a vertical portion and a pair of horizontal portions adjoined to the vertical portion and laterally extending from the vertical portion and vertically spaced from each other;
the vertical portion of the first conductive material portion has a first thickness between a pair of vertical sidewalls including a first sidewall and a second sidewall;
each of the pair of horizontal portions of the first conductive material portion has a second thickness between a respective pair of substantially horizontal surfaces; and
the first thickness is greater than the second thickness.

2. The three-dimensional memory device of claim 1 , wherein:
the first conductive material portion comprises a material selected from ruthenium, gold, silver or copper; and
the second conductive material portion comprises a material selected from tungsten, titanium or chromium.

3. The three-dimensional memory device of claim 2 , wherein:
the first conductive material portion comprises ruthenium; and
the second conductive material portion comprises tungsten.

4. The three-dimensional memory device of claim 2 , wherein:
the first sidewall of the first conductive material portion contacts a portion of an outer sidewall of the memory film; and
the second sidewall of the first conductive material portion contacts an inner sidewall of the second conductive material portion.

5. The three-dimensional memory device of claim 1 , wherein the second conductive material portion is spaced from the insulator layers and the memory film by the first conductive material portion.

6. The three-dimensional memory device of claim 1 , wherein each of the electrically conductive layers further comprises a third conductive material portion comprising another tensile-stress-generating metallic material contacting a sidewall of the second conductive material portion.

7. The three-dimensional memory device of claim 6 , wherein the third conductive material portion comprises a material selected from ruthenium, gold, silver or copper.

8. The three-dimensional memory device of claim 1 , further comprising a metallic liner in contact with a sidewall of the memory film, a bottom surface of an overlying insulator layer, and a top surface of an underlying insulator layer, wherein an inner sidewall of the second conductive material portion is in contact with the metallic liner.

9. The three-dimensional memory device of claim 1 , wherein the electrically conductive layers comprise:
a first control gate electrode located in a first device level; and
a second control gate electrode located in a second device level that is located below the first device level.

10. The three-dimensional memory device of claim 9 , wherein:
the first conductive material portion comprises a ruthenium portion; and
each ruthenium portion is located within one device level of the stack, and is disjoined from other ruthenium portions located at any other device level of the stack.

11. The three-dimensional memory device of claim 10 , wherein each ruthenium portion contacts an entire bottom surface of an overlying insulator layer and an entire top surface of an underlying insulator layer.

12. The three-dimensional memory device of claim 1 , wherein the memory film comprises a stack including a blocking dielectric, at least one charge storage element, and a tunneling dielectric.

13. The three-dimensional memory device of claim 1 , wherein:
the three-dimensional memory device comprises a vertical NAND device located in a device region; and
the electrically conductive layers comprise, or are electrically connected to a respective word line of the NAND device.

14. The three-dimensional memory device of claim 13 , wherein:
the device region comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to the top surface of the substrate;
a plurality of charge storage regions, each charge storage region located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level;
the electrically conductive layers in the stack comprise or are in electrical contact with the plurality of control gate electrodes and extend from the device region to a contact region including a plurality of electrically conductive via connections; and
the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

15. The three-dimensional memory device of claim 1 , wherein the first sidewall is in physical contact with the memory film.

16. The three-dimensional memory device of claim 15 , wherein the second sidewall is in physical contact with a sidewall of the second conductive material portion.

17. The three-dimensional memory device of claim 1 , wherein:
the insulating layers comprise silicon oxide; and
the memory film comprises a blocking dielectric comprising a material less hydrophilic than silicon oxide and contacting the first conductive material portion.

18. The three-dimensional memory device of claim 17 , wherein the blocking dielectric comprise silicon nitride.

19. The three-dimensional memory device of claim 17 , wherein the first conductive material portion consists essentially of ruthenium.

20. The three-dimensional memory device of claim 1 , wherein:
the first thickness is in a range from 3 nm to 12 nm; and
the second thickness is in a range from 1 nm to 7 nm.

21. The three-dimensional memory device of claim 1 , wherein:
a memory opening extends through an entirety of the alternating stack;
the memory film comprises a blocking dielectric contacting an entirety of a sidewall of the memory opening that extends from a bottommost layer of the alternating stack to a topmost layer of the alternating stack.

22. The three-dimensional memory device of claim 1 , wherein the second conductive material portion comprises a vertical portion and a pair of horizontal portions adjoined to the vertical portion of the second conductive material portion and laterally extending from the vertical portion of the second conductive material portion and vertically spaced from each other.

23. The three-dimensional memory device of claim 22 , wherein:
each of the electrically conductive layers further comprises a third conductive material portion; and
the third conductive material portion comprises a vertical portion and a pair of horizontal portions

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Sharangpani Rahul
• Makala Raghuveer S
• Matamis George

Classifications

• H01L27/11582

  Electricity · mapped topic

• H01L27/11578

  Electricity · mapped topic

• H01L27/11524

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic