Ultra-thin, hyper-density semiconductor packages

Patent metadata

Field	Value
Publication number	US-11430724-B2
Application number	US-201716646529-A
Country	US
Kind code	B2
Filing date	Dec 30, 2017
Priority date	Dec 30, 2017
Publication date	Aug 30, 2022
Grant date	Aug 30, 2022

Abstract

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a substrate;
a plurality of metal pillars on a top surface of the substrate;
a semiconductor component disposed on the substrate, the semiconductor component comprising one or more dies, and the semiconductor component having a top surface;
a mold compound encapsulating the plurality of metal pillars and the semiconductor component, the mold compound having an uppermost surface above the top surface of the semiconductor component, wherein the mold compound is not vertically over the semiconductor component;
an interposer coupled to the plurality of metal pillars, the interposer above the uppermost surface of the mold compound;
a first die and a second die coupled to the interposer, the first die laterally spaced apart from the second die, the first die vertically over a first one of the plurality of metal pillars at a first side of the semiconductor component, and the second die vertically over a second one of the plurality of metal pillars at a second side of the semiconductor component, the second side opposite the first side; and
a plurality of solder bumps on a bottom surface of the substrate.

2. The semiconductor package of claim 1 , wherein each metal pillar includes a solder cap that is partially encapsulated by the mold compound and wherein the interposer is coupled to the plurality of metal pillars via the solder caps.

3. The semiconductor package of claim 1 , wherein a z-height of the package is less than or equal to 1 mm.

4. The semiconductor package of claim 1 , wherein a z-height of the package is approximately 869 μm to 915 μm.

5. The semiconductor package of claim 1 , wherein a die-to-package height ratio for the package is equal to or greater than 0.7.

6. The semiconductor package of claim 1 , wherein the plurality of metal pillars has a pitch that is greater than or equal to 150 μm.

7. The semiconductor package of claim 1 , wherein a second package is disposed on interposer.

8. The semiconductor package of claim 1 , wherein a z-height of the substrate is approximately 66 μm.

9. The semiconductor package of claim 1 , wherein a z-height of the semiconductor component is approximately 125 μm.

10. The semiconductor package of claim 1 , wherein a z-height of the interposer is approximately 63 μm.

11. A semiconductor package, comprising:
a substrate;
an epoxy layer disposed on a top surface of the substrate;
a plurality of metal pillars on a top surface of the substrate;
a semiconductor component disposed on the epoxy layer, the semiconductor component having a top surface;
a mold compound encapsulating the epoxy layer and the semiconductor component, the mold compound having an uppermost surface above the top surface of the semiconductor component, wherein the mold compound is not vertically over the semiconductor component;
a metallization layer on the uppermost surface of the mold compound and over the semiconductor component, the metallization layer above the uppermost surface of the mold compound;
a first die and a second die coupled to the metallization layer, the first die laterally spaced apart from the second die, the first die vertically over a first one of the plurality of metal pillars at a first side of the semiconductor component, and the second die vertically over a second one of the plurality of metal pillars at a second side of the semiconductor component, the second side opposite the first side; and; and
a plurality of solder bumps on a bottom surface of the substrate.

12. The semiconductor package of claim 11 , wherein the semiconductor component comprises one or more semiconductor dies.

13. The semiconductor package of claim 11 , wherein a z-height of the package is less than or equal to 1 mm.

14. The semiconductor package of claim 11 , wherein a z-height of the package is approximately 425 μm to 750 μm.

15. The semiconductor package of claim 11 , wherein a die-to-package height ratio for the package is equal to or greater than 0.7.

16. The semiconductor package of claim 11 , wherein the epoxy layer has a z-height that is approximately 35 μm.

17. The semiconductor package of claim 11 , wherein the metallization layer has a z-height that is approximately 30 μm to 100 μm.

18. The semiconductor package of claim 11 , wherein a z-height of the plurality of solder bumps is approximately 100 μm to 150 μm.

19. The semiconductor package of claim 11 , wherein a z-height of the semiconductor component is approximately 110 μm to 300 μm.

20. The semiconductor package of claim 11 , wherein a z-height of the substrate is approximately 150 μm to 180 μm.

21. A method of forming a semiconductor package, comprising:
forming a plurality of metal pillars on a top surface of a substrate;
disposing a semiconductor component on the top surface of the substrate, the semiconductor component having a top surface;
encapsulating the plurality of metal pillars and the semiconductor component in a mold compound, the mold compound having an uppermost surface above the top surface of the semiconductor component, wherein the mold compound is not vertically over the semiconductor component;
coupling an interposer to one or more of the plurality of metal pillars and the semiconductor component, the interposer above the uppermost surface of the mold compound;
coupling a first die and a second die to the interposer, the first die laterally spaced apart from the second die, the first die vertically over a first one of the plurality of metal pillars at a first side of the semiconductor component, and the second die vertically over a second one of the plurality of metal pillars at a second side of the semiconductor component, the second side opposite the first side; and
forming a plurality of solder bumps on a bottom surface of the substrate.

22. The method of claim 21 , further comprising disposing a second package on the interposer.

23. The method of claim 21 , wherein a z-height of the package is approximately 869 μm to 915 μm.

24. The method of claim 21 , further comprising:
forming, in each metal pillar, a solder cap that is partially encapsulated by the mold compound, wherein the interposer is coupled to the plurality of metal pillars via the solder caps.

Assignees

• Intel Corp

Inventors

• Mallik Debendra
• Sankman Robert L
• Nickerson Robert
• Modi Mitul
• Ganesan Sanka
• Swaminathan Rajasekaran
• Karhade Omkar
• Liff Shawna M
• Alur Amruthavalli
• Chavali Sri Chaitra J

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title