Solder grid array for attachment of a die package
US-12557683-B2 · Feb 17, 2026 · US
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Nickerson Robert patents
Nickerson Robert is listed as an inventor on 21 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Nickerson Robert |
| Total patents | 21 |
| First publication | Jun 2, 2015 |
| Latest publication | Feb 17, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Ultra-thin, hyper-density semiconductor packages
US-2025391754-A1 · Dec 25, 2025 · US
Ultra-thin, hyper-density semiconductor packages
US-12476174-B2 · Nov 18, 2025 · US
Ultra-thin, hyper-density semiconductor packages
US-12406914-B2 · Sep 2, 2025 · US
Ultra-thin, hyper-density semiconductor packages
US-2024030116-A1 · Jan 25, 2024 · US
Solder grid array for attachment of a die package
US-2023197659-A1 · Jun 22, 2023 · US
Ultra-thin, hyper-density semiconductor packages
US-2023138543-A1 · May 4, 2023 · US
Ultra-thin, hyper-density semiconductor packages
US-2022344247-A1 · Oct 27, 2022 · US
Micro-trenching mold interface in a pop package
US-11462527-B2 · Oct 4, 2022 · US
Ultra-thin, hyper-density semiconductor packages
US-11430724-B2 · Aug 30, 2022 · US
Recent patents
Latest publications not already listed above.
Ultra-thin, hyper-density semiconductor packages
US-2020273784-A1 · Aug 27, 2020 · US
Offset interposers for large-bottom packages and large-die package-on-package structures
US-2020251462-A1 · Aug 6, 2020 · US
Micro-trenching mold interface in a pop package
US-2020035658-A1 · Jan 30, 2020 · US
Substrate architecture for solder joint reliabilty in microelectronic package structures and methods of forming the same
US-2019104610-A1 · Apr 4, 2019 · US
Methods of forming trenches in packages structures and structures formed thereby
US-10231338-B2 · Mar 12, 2019 · US
Methods for solder for through-mold interconnect
US-9666549-B2 · May 30, 2017 · US
Methods of forming trenches in packages structures and structures formed thereby
US-2016381800-A1 · Dec 29, 2016 · US
Tall solders for through-mold interconnect
US-2016043049-A1 · Feb 11, 2016 · US
Package substrates with multiple dice
US-9177911-B2 · Nov 3, 2015 · US
Tall solders for through-mold interconnect
US-9159690-B2 · Oct 13, 2015 · US
Processes of making pad-less interconnect for electrical coreless substrate
US-9049807-B2 · Jun 2, 2015 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Intel Corp | 21 |
| Soto Javier | 1 |
| Gurumurthy Charan | 1 |
| Nickerson Robert | 1 |
| Mallik Debendra | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10W90/701 | 19 |
| H10W90/00 | 18 |
| H10W90/724 | 16 |
| H10W74/117 | 16 |
| H10W90/722 | 15 |