System in package fan out stacking architecture and process flow

US9633974B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9633974-B2
Application numberUS-201514638925-A
CountryUS
Kind codeB2
Filing dateMar 4, 2015
Priority dateMar 4, 2015
Publication dateApr 25, 2017
Grant dateApr 25, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

First claim

Opening claim text (preview).

What is claimed is: 1. A package comprising: a first die including a bottom surface that includes a first contact pad and a passivation layer; a first redistribution layer (RDL); wherein the first die is attached to a front side of the first RDL such that the front side of the first RDL is directly on the first contact pad and the passivation layer; a first molding compound encapsulating the first die on the front side of the first RDL; a top surface of a second die attached to a back side of the first RDL with a die attach film such that the second die is facing back to the first RDL; a second RDL; a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL; a second molding compound encapsulating the second die and the plurality of conductive pillars between the back side of the first RDL and the front side of the second RDL. 2. The package of claim 1 , further comprising a plurality of conductive bumps on a back side of the second RDL. 3. The package of claim 1 , wherein the first molding compound does not completely cover a top surface of the first die. 4. The package of claim 3 , wherein the second molding compound does not completely cover a bottom surface of the second die adjacent the second RDL. 5. The package of claim 1 , wherein the second RDL comprises a second redistribution line formed directly on one of the plurality of conductive pillars. 6. The package of claim 5 , wherein the die attach film is a cured film. 7. The package of claim 5 , wherein the second RDL comprises a third redistribution line formed directly on a conductive contact of the second die. 8. The package of claim 5 , wherein a bottom surface of a conductive contact of the second die, and bottom surfaces of the plurality of conductive pillars are coplanar. 9. A package comprising: a first element including a bottom surface that includes a first contact pad and a passivation layer; a first redistribution layer (RDL); wherein the first element is attached to a front side of the first RDL such that the front side of the first RDL is directly on the first contact pad and the passivation layer; a first molding compound encapsulating the first element on the front side of the first RDL; a top surface of a second die attached to a back side of the first RDL with a die attach film such that the second die is facing back to the first RDL; a second RDL; a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL; a second molding compound encapsulating the second die and the plurality of conductive pillars between the back side of the first RDL and the front side of the second RDL. 10. The package of claim 9 , wherein the second die is a logic die. 11. The package of claim 10 , wherein the first element is a memory die. 12. The package of claim 9 , wherein the first RDL is less than 50 μm thick. 13. The package of claim 9 , wherein the second RDL is less than 50 μm thick. 14. The package of claim 9 , wherein the second RDL comprises a second redistribution line formed directly on one of the plurality of conductive pillars. 15. The package of claim 9 , wherein the second RDL comprises redistribution lines formed directly on one of the plurality of conductive pillars, and directly on a conductive contact of the second die. 16. The package of claim 15 , wherein the die attach film is a cured film.

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • of bump connectors · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

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Frequently asked questions

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What does patent US9633974B2 cover?
Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification H10W74/121. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 25 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).