Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP

Patent metadata

Field	Value
Publication number	US-9385009-B2
Application number	US-201113243558-A
Country	US
Kind code	B2
Filing date	Sep 23, 2011
Priority date	Sep 23, 2011
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.

First claim

What is claimed:

1. A method of making a semiconductor device, comprising:
providing a semiconductor die including a contact pad formed on a surface of the semiconductor die;
depositing an encapsulant around the semiconductor die;
forming a first insulating layer in contact with a first surface of the encapsulant and the semiconductor die;
forming a first via through the first insulating layer extending to the contact pad of the semiconductor die;
forming a second via through the first insulating layer and extending to expose the encapsulant;
forming a first conductive layer over the first insulating layer and into the first via and second via to electrically connect to the contact pad of the semiconductor die;
forming a conductive via through a second surface of the encapsulant opposite the first surface of the encapsulant and aligned with the second via and extending to the first conductive layer after forming the first conductive layer;
forming a second insulating layer in contact with the first insulating layer and first conductive layer;
forming a third via through the second insulating layer and aligned with the second via and extending to the first conductive layer;
forming a second conductive layer over the second insulating layer and into the third via over the first conductive layer in the second via; and
forming a bump to contact the second conductive layer in the third via.

2. The method of claim 1 , further including forming the first, second, and third vias by laser direct ablation.

3. The method of claim 1 , further including disposing a discrete device adjacent to the semiconductor die prior to forming the encapsulant.

4. The method of claim 1 , further including:
stacking a plurality of semiconductor devices; and
electrically connecting the stacked semiconductor devices through the first and second conductive layers.

5. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around the semiconductor die;
forming a first insulating layer in contact with a first surface of the encapsulant and the semiconductor die;
forming a first via extending through the first insulating layer to expose the encapsulant;
forming a first conductive layer over the first insulating layer and into the first via to contact the encapsulant;
forming a conductive via through a second surface of the encapsulant opposite the first surface of the encapsulant and aligned with the first via and extending to the first conductive layer;
forming a second insulating layer in contact with the first insulating layer and first conductive layer;
forming a second via through the second insulating layer and aligned with the first via and extending to the first conductive layer; and
forming a second conductive layer into the second via over the first conductive layer in the first via.

6. The method of claim 5 , further including forming the first and second vias by laser direct ablation.

7. The method of claim 5 , further including:
forming a channel in the first insulating layer; and
forming the first conductive layer within the channel and first via.

8. The method of claim 5 , further including:
stacking a plurality of semiconductor devices; and
electrically connecting the stacked semiconductor devices through the first conductive layer.

9. The method of claim 5 , further including:
providing a semiconductor package; and
stacking the semiconductor package over the semiconductor device.

10. The method of claim 5 , further including:
forming a third via through the encapsulant and extending to the semiconductor die; and
depositing a conductive material in the third via.

11. The method of claim 5 , further including forming a bump to contact the second conductive layer in the second via.

12. The method of claim 11 , wherein the conductive via extends to the bump.

13. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around the semiconductor die and coplanar with an active surface of the semiconductor die;
forming a first insulating layer over a first surface of the encapsulant and the semiconductor die;
forming a first via through the first insulating layer and extending to the encapsulant;
forming a first conductive layer over the first insulating layer and into the first via;
forming a second insulating layer over the first insulating layer and first conductive layer;
forming a second via through the second insulating layer and aligned with the first via and extending to the first conductive layer; and
forming a second conductive layer into the second via to contact the first conductive layer in the first via.

14. The method of claim 13 , further including forming the first and second vias by laser direct ablation.

15. The method of claim 13 , further including forming a conductive via through the encapsulant and aligned with the first via and extending to the first conductive layer.

16. The method of claim 13 , further including:
stacking a plurality of semiconductor devices; and
electrically connecting the stacked semiconductor devices through the first conductive layer.

17. The method of claim 13 , further including forming a bump to contact the second conductive layer in the second via.

18. The method of claim 13 , further including:
forming a third via through the encapsulant and extending to the semiconductor die; and
depositing a conductive material in the third via.

19. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around the semiconductor die;
forming a first insulating layer over the semiconductor die and a first surface of the encapsulant;
forming a first conductive layer over the first insulating layer and extending through the first insulating layer to contact the encapsulant; and
forming a conductive via through a second surface of the encapsulant opposite the first surface of the encapsulant and extending to the first conductive layer after forming the first conductive layer.

20. The method of claim 19 , further including:
stacking a plurality of semiconductor devices; and
electrically connecting the stacked semiconductor devices through the conductive via.

21. The method of claim 19 , wherein forming the conductive via further includes:
forming a via through the encapsulant by laser direct ablation; and
depositing a conductive material into the via.

22. The method of claim 19 , further including forming an interconnect structure over a portion of the first conductive layer extending through the first insulating layer.

23. The method of claim 19 , further including:
forming a second insulating layer over the first insulating layer and first conductive layer; and
forming a second conductive layer over the first conductive layer.

24. The method of claim 19 , further including:
forming a via through the encapsulant and extending to the semiconductor die; and
depositing a conductive material in the via.

Assignees

• Lin Yaojian
• Huang Rui
• Cheng Kang
• Yu Gu
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Huang Rui
• Cheng Kang
• Yu Gu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9226

  with via interconnections · CPC title