Pad design for reliability enhancement in packages

US9824990B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9824990-B2
Application numberUS-201514865832-A
CountryUS
Kind codeB2
Filing dateSep 25, 2015
Priority dateJun 12, 2014
Publication dateNov 21, 2017
Grant dateNov 21, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.

First claim

Opening claim text (preview).

What is claimed is: 1. A package comprising: a first package comprising: a corner; a device die; a molding material molding the device die therein; and a plurality of bonding pads comprising: a corner bonding pad at the corner, wherein the corner bonding pad is elongated in a top view of the first package; and an additional bonding pad, wherein the additional bonding pad is non-elongated, wherein the corner bonding pad and the additional bonding pad have a same top-view area. 2. The package of claim 1 , wherein the plurality of bonding pads comprises a plurality of non-elongated bonding pads encircling a region free from bonding pads, wherein the region has a top-view area greater than an area occupied by an array comprising at least four bonding pads. 3. The package of claim 2 , wherein all bonding pads immediately neighboring the region are non-elongated bonding pads. 4. The package of claim 1 further comprising a dielectric layer on a backside of the device die, wherein the corner bonding pad comprises a first portion in the dielectric layer, and a second portion protruding beyond the dielectric layer. 5. The package of claim 4 further comprising: a die-attach film comprising a first surface contacting the device die, wherein the dielectric layer forms an interface with the die-attach film and the molding material, and the interface continuously and smoothly extends from the die-attach film to one of the plurality of bonding pads. 6. The package of claim 1 further comprising: a second package; and a first solder region bonding the corner bonding pad to the second package; and a second solder region bonding the additional bonding pad to the second package. 7. The package of claim 6 , wherein the second package comprises a metal pad in contact with the first solder region, wherein the metal pad is elongated. 8. The package of claim 6 , wherein the first solder region and the second solder region are in contact with a sidewall of the corner bonding pad and a sidewall of the additional bonding pad, respectively. 9. The package of claim 8 , wherein the second package comprises a first and a second metal pad in contact with the first solder region and the second solder region, respectively, wherein the first metal pad is elongated, and the second metal pad is non-elongated. 10. A package comprising: a first package comprising: a corner; a device die comprising a front side and a backside; a molding material molding the device die therein; a die-attach film comprising a surface contacting the device die; a dielectric layer on the backside of the device die; a plurality of bonding pads, with each of the plurality of bonding pads comprising a portion in the dielectric layer, wherein the dielectric layer forms an interface with the die-attach film and the molding material, and the interface extends from the die-attach film to one of the plurality of bonding pads, and wherein the plurality of bonding pads comprises: a corner bonding pad at the corner, wherein the corner bonding pad is elongated in a top view of the first package, and is centripetal, with a lengthwise direction extending toward a center of the first package; and an additional bonding pad farther away from the corner than the corner bonding pad, wherein the additional bonding pad is non-elongated in the top view of the first package; a first solder region bonded to the corner bonding pad; and a second solder region bonded to the additional bonding pad. 11. The package of claim 10 comprising an elongated bonding pad at each corner of the first package. 12. The package of claim 10 further comprising: a second package, with the first and the second solder regions bonding the first package to the second package. 13. The package of claim 12 , wherein the second package comprises a first and a second metal pad in contact with the first solder region and the second solder region, respectively, and wherein the first metal pad is elongated, and the second metal pad is non-elongated. 14. The package of claim 10 , wherein the first solder region and the second solder region are in contact with sidewalls of the corner bonding pad and the additional bonding pad, respectively. 15. The package of claim 10 , wherein the corner bonding pad and the additional bonding pad have a same top-view area. 16. A package comprising: a first package comprising: a through-via; an encapsulating material encapsulating the through-via therein; a dielectric layer on a side of the encapsulating material; a plurality of bonding pads at a surface of the dielectric layer, wherein the plurality of bonding pads comprises: a first bonding pad, wherein the first bonding pad is elongated in a top view of the first package, and is centripetal, with a lengthwise direction extending toward a center of the first package; and a second bonding pad at a same level as the first bonding pad, wherein the second bonding pad is non-elongated in the top view of the first package, and the first bonding pad and the second bonding pad have a same top-view area; a first solder region bonded to the first bonding pad; a second solder region bonded to the second bonding pad; and a second package, with the first and the second solder regions bonding the first package to the second package, wherein the second package comprises: a third bonding pad bonded to the first solder region; and a fourth bonding pad bonded to the second solder region, wherein both the third bonding pad and the fourth bonding pad are non-elongated in a top view of the second package. 17. The package of claim 16 , wherein the first bonding pad is closest to a corner of the first package than all other bonding pads in the first package. 18. The package of claim 16 , wherein the first solder region is in physical contact with edges of the first bonding pad. 19. The package of claim 16 further comprising: a device die encapsulated in the encapsulating material; and a die-attach film comprising a surface contacting the device die, wherein the dielectric layer forms an interface with the die-attach film and the encapsulating material, and the interface continuously and smoothly extends from the die-attach film to one of the plurality of bonding pads. 20. The package of claim 16 further comprising a via in the dielectric layer, wherein the via physically connects one of the first bonding pad and the second bonding pad to the through-via.

Assignees

Inventors

Classifications

  • by chemical means · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between stacked chips · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

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Frequently asked questions

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What does patent US9824990B2 cover?
A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/65. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 21 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).