Structure and method for interconnection

Patent metadata

Field	Value
Publication number	US-9698100-B2
Application number	US-201514829851-A
Country	US
Kind code	B2
Filing date	Aug 19, 2015
Priority date	Aug 19, 2015
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

The present disclosure provides a method of fabricating an integrated circuit in accordance with some embodiments. The method includes providing a substrate having a first conductive feature in a first dielectric material layer; selectively etching the first conductive feature, thereby forming a recessed trench on the first conductive feature; forming an etch stop layer on the first dielectric material layer, on the first conductive feature and sidewalls of the recessed trench; forming a second dielectric material layer on the etch stop layer; forming an opening in the second dielectric material layer; and forming a second conductive feature in the opening of the second dielectric material layer. The second conductive feature is electrically connected with the first conductive feature.

First claim

What is claimed is:

1. A method of fabricating an integrated circuit, comprising:
providing a substrate having a first conductive feature in a first dielectric material layer;
selectively etching the first conductive feature, thereby forming a recessed trench on the first conductive feature;
forming an etch stop layer on the first dielectric material layer, on the first conductive feature and sidewalls of the recessed trench;
forming a second dielectric material layer on the etch stop layer;
forming a first patterned mask layer on the second dielectric material layer;
removing a first portion of the second dielectric material layer through the first patterned mask layer to form a first trench extending through the second dielectric material layer, wherein a bottom surface of the first trench is defined by a second portion of the second dielectric material layer;
removing the first patterned mask layer;
after removing the first patterned mask layer, removing the second portion of the second dielectric material layer from within the first trench such that the first trench is extended to at least the etch stop layer; and
forming a second conductive feature in the extended first trench, wherein the second conductive feature is electrically connected with the first conductive feature.

2. The method of claim 1 , wherein the providing of the substrate includes
depositing the first dielectric material layer on the substrate;
forming a second trench in the first dielectric material layer;
filling a metal in the second trench; and
performing a chemical mechanical polishing (CMP) process to the metal and first dielectric material layer such that a top surface of the first conductive feature is substantially coplanar with a top surface of the first dielectric material layer.

3. The method of claim 2 , wherein removing the first portion of the second dielectric material layer through the first patterned mask layer to form the first trench extending through the second dielectric material layer includes:
performing a first etching process to the second dielectric material layer.

4. The method of claim 1 , wherein the selectively etching of the first conductive feature partially removes the first conductive feature such that the first conductive feature has a recessed top surface lower than the top surface of the first dielectric material layer.

5. The method of claim 4 , wherein
the first conductive feature includes copper; and
the selectively etching of the first conductive feature includes a dry etching process with etching gas selected from the group consisting of CH4, H2 and a combination thereof.

6. The method of claim 5 , wherein the selectively etching of the first conductive feature includes a dry etching process using a gas selected from the group consisting of a mixture of CH4 and Ar; a mixture of CH4 and N2; a mixture of H2 and Ar; a mixture of H2 and N2, and a combination thereof.

7. The method of claim 1 , wherein the providing of the substrate includes
depositing the first dielectric material layer on the substrate;
forming a second trench in the first dielectric material layer;
filling a conductive material in the second trench; and
performing a chemical mechanical polishing (CMP) process to the first conductive material and the first dielectric material layer such that a top surface of the first conductive feature is substantially coplanar with a top surface of the first dielectric material layer.

8. The method of claim 1 , wherein the etch stop layer is substantially conformal to the recessed trench and has a dip in the recessed trench.

9. The method of claim 1 , wherein the second dielectric material layer includes a low k dielectric material film and a nitrogen free anti-reflective coating (NFARC) film on the low k dielectric material layer.

10. The method of claim 2 , wherein the first conductive feature is a metal line; and the second conductive feature is a via feature landing on the metal line.

11. A method of fabricating an integrated circuit, comprising:
providing a substrate having an underlying conductive feature embedded in a first dielectric material layer;
selectively etching the underlying conductive feature, thereby forming a recessed trench in the first dielectric material layer, wherein the recessed trench is vertically aligned with the underlying conductive feature;
forming an etch stop layer on the first dielectric material layer, the underlying conductive feature and sidewalls of the recessed trench;
forming a second dielectric material layer on the etch stop layer;
forming a first patterned mask on the second dielectric material layer, wherein the first patterned mask includes a first opening that defines a first region for an overlying conductive feature;
forming a second patterned mask on the second dielectric material layer, wherein the second patterned mask includes a second opening that defines a second region for a via feature;
performing a first etching process to the second dielectric material layer through the second opening of the second patterned mask, thereby recessing the second dielectric material layer within the second opening;
removing the second patterned mask;
performing a second etching process to the second dielectric material layer through the first opening of the first patterned mask, thereby forming a via opening in a lower portion of the second dielectric material layer and a trench in an upper portion of the second dielectric material layer; and
filling in the trench and via opening with a conductive material, thereby forming the via feature in the via opening and the overlying conductive feature in the trench of the second dielectric material layer, wherein the via feature electrically connects the underlying conductive feature and the overlying conductive feature.

12. The method of claim 11 , wherein
the forming of the first patterned mask includes forming a patterned hard mask by a first procedure that includes depositing a hard mask material layer; forming a patterned resist layer by a first lithography process; and etching the hard mask material layer; and
the forming of the second patterned mask includes forming a patterned resist layer by a second lithography process.

13. The method of claim 11 , wherein the selectively etching of the first conductive feature partially removes the first conductive feature such that the first conductive feature has a recessed top surface lower than a top surface of the first dielectric material layer.

14. The method of claim 11 , wherein the forming of the etch stop layer includes depositing the etch stop layer in the recessed trench, wherein the etch stop layer is substantially conformal to the recessed trench and the etch stop layer is different from the second dielectric material layer in composition such that the second etching process stops on the etch stop layer.

15. A method comprising:
forming a first conductive feature in a first dielectric layer;
removing a first portion of the first conductive feature to form a first trench within the first dielectric layer, wherein a second portion of the first conductive feature remains disposed within the first dielectric layer after the removal of the first portion of the first conductive feature;
forming an etch stop layer along a sidewall of the first trench and over the second portion of the first conductive feature;
forming a second dielectric layer within the first trench;
forming a first patterned mask layer on the second dielectric layer;
removing a first portion of the second dielectric layer through the first patterned mask

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lu Chih Wei
• Lee Chung-Ju
• Bao Tien-I

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/093

  by modifying materials of the dielectric parts · CPC title