Semiconductor fabrication method for producing nano-scaled electrically conductive lines

Patent metadata

Field	Value
Publication number	US-11264271-B2
Application number	US-202017081337-A
Country	US
Kind code	B2
Filing date	Oct 27, 2020
Priority date	Dec 19, 2019
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A method is provided for producing electrically conductive lines (23a, 23b), wherein spacers are deposited on a sacrificial structure present on a stack of layers, including a hardmask layer on top of a dielectric layer into which the lines are to be embedded, and an intermediate layer on top of the hardmask layer. A self-aligned litho-etch step is then performed to create an opening in the intermediate layer, the opening being self-aligned to the space between two adjacent sidewalls of the sacrificial structure. This self-aligned step precedes the deposition of spacers on the sacrificial structure, so that spacers are also formed on the transverse sidewalls of the opening, i.e. perpendicular to the spacers on the walls of the sacrificial structure. A blocking material is provided in the area of the bottom of the opening that is surrounded on all sides by spacers, thereby creating a block with a reduced size.

First claim

The invention claimed is:

1. A method for producing electrically conductive lines on a planar substrate, embedded in a dielectric material, wherein at least two colinear lines are separated by a dielectric gap between tips of said two lines, the method comprising the following steps:
producing a mask layer on a layer of the dielectric material formed on the planar substrate;
producing an intermediate layer on top of and in contact with the mask layer;
producing a sacrificial structure on the intermediate layer, the sacrificial structure comprising at least two parallel and mutually facing sidewalls of the structure with an elongate open area between said sidewalls, the open area extending in an X-direction of an orthogonal X-Y axis system in a plane parallel to the substrate;
by a lithography and etch process, producing an essentially rectangular opening in the intermediate layer, thereby locally exposing the mask layer, wherein
the size of the opening in an Y-direction is self-aligned relative to the two parallel sidewalls, and
the size (D) of the opening in an X-direction is defined by a mask pattern applied in the lithography and etch process;

depositing a layer of spacer material conformally on the sacrificial structure and on a bottom and sidewalls of the opening;
etching back the spacer material so as to expose a top of the sacrificial structure, thereby creating:
two high spacers extending in the X-direction on the two parallel sidewalls, and
two low spacers extending in the Y-direction on the two sidewalls of the opening extending in said Y-direction, wherein the mask layer is exposed in an area of the bottom of the opening, said area being surrounded by the two low spacers and by the two high spacers;

removing the sacrificial structure selectively with respect to the spacers;
depositing a blocking material on the exposed area of the mask layer; using the high and low spacers and the blocking material as a mask for patterning the intermediate layer and the mask layer, thereby creating a patterned mask on the layer of the dielectric material;
etching trenches in the layer of the dielectric material, in accordance with the patterned mask; and
filling the trenches with an electrically conductive material and planarizing said electrically conductive material, thereby obtaining the two colinear conductive lines separated by the dielectric gap at a location of the blocking material.

2. The method according to claim 1 , wherein the sacrificial structure is an array of mutually parallel mandrel lines, and wherein the two parallel sidewalls of the sacrificial structure are the mutually facing sidewalls of two adjacent mandrel lines.

3. The method according to claim 1 , wherein the sidewalls of the opening in the intermediate layer, extending in the Y-direction are slanted inward toward the middle of the opening, so that the width in the X-direction of an exposed area of the mask layer is reduced compared to a case wherein said sidewalls of the opening are vertical.

4. The method according to claim 1 , wherein the mask layer is a titanium nitride layer and the intermediate layer is a layer of silicon nitride.

5. The method according to claim 1 , wherein a width of the dielectric gap in the X-direction is lower than 18 nm.

6. The method according to claim 1 , wherein a width of the dielectric gap in the X-direction is lower than 10 nm.

7. The method according to claim 1 , wherein a width of the dielectric gap in the X-direction is lower than 5 nm.

8. The method according to claim 1 , wherein the blocking material is ruthenium, titanium oxide or platinum.

9. The method according to claim 8 , wherein the blocking material is ruthenium.

10. The method according to claim 1 , wherein the mask layer is a titanium nitride layer, the intermediate layer is a layer of silicon nitride, and the blocking material is ruthenium.

Assignees

• Imec Vzw

Inventors

• O'Toole Martin
• Tokei Zsolt
• Wilson Christopher
• Decoster Stefan

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title