Backside power rail and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11222892-B2
Application number	US-202016901963-A
Country	US
Kind code	B2
Filing date	Jun 15, 2020
Priority date	Jun 15, 2020
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a first epitaxial feature and a second epitaxial feature;
a plurality of channel members extending between the first epitaxial feature and the second epitaxial feature;
a gate structure wrapping around each of the plurality of channel members;
a bottom dielectric feature disposed over the gate structure;
a first liner over the first epitaxial feature and a portion of the bottom dielectric feature;
a dielectric layer disposed over the first liner;
a silicide feature on and in direct contact with the second epitaxial feature;
a backside contact over and in direct contact with the silicide feature; and
a conductive line disposed over the dielectric layer and the backside contact.

2. The semiconductor structure of claim 1 , wherein sidewalls of the backside contact are lined by a second liner.

3. The semiconductor structure of claim 2 , wherein a thickness of the second liner is smaller than a thickness of the first liner.

4. The semiconductor structure of claim 1 , wherein a portion of the backside contact extends through the bottom dielectric feature.

5. The semiconductor structure of claim 1 , wherein a portion of the first liner and a portion of the dielectric layer extend through the bottom dielectric feature.

6. The semiconductor structure of claim 1 , wherein a portion of the backside contact is disposed over the bottom dielectric feature.

7. The semiconductor structure of claim 1 , wherein the silicide feature comprises a metal silicide and a metal silicide nitride.

8. A method, comprising:
providing a workpiece comprising:
a first epitaxial feature and a second epitaxial feature,
a plurality of channel members extending between the first epitaxial feature and the second epitaxial feature,
a gate structure wrapping around each of the plurality of channel members,
a bottom dielectric feature disposed over the gate structure,
a first substrate portion over the first epitaxial feature, and
a second substrate portion over the second epitaxial feature;

selectively recessing the first substrate portion to expose the first epitaxial feature;
depositing a first liner over the workpiece and the first epitaxial feature;
depositing a first dielectric layer over the first liner; and
planarizing the workpiece such that top surfaces of the first dielectric layer and the second substrate portion are coplanar.

9. The method of claim 8 , wherein the selectively recessing to expose the first epitaxial feature comprises recessing the first epitaxial feature.

10. The method of claim 8 , further comprising:
selectively recessing the second substrate portion to expose the second epitaxial feature in a backside contact trench;
depositing a second liner over the workpiece and the backside contact trench;
anisotropically recessing the second liner to expose a portion the second epitaxial feature;
forming a silicide feature on the exposed portion of the second epitaxial feature; and
depositing a metal material in the backside contact trench to form a backside contact.

11. The method of claim 10 , further comprising:
planarizing the first dielectric layer, the first liner, the second liner, and the backside contact to form a planar surface;
depositing a second dielectric layer on the planar surface; and
forming a conductive line in the second dielectric layer such that the conductive line is in direct contact with the backside contact.

12. The method of claim 10 , wherein the selectively recessing the second substrate portion to expose the second epitaxial feature comprises recessing the second epitaxial feature.

13. The method of claim 10 , wherein a thickness of the second liner is smaller than a thickness of the first liner.

14. The method of claim 10 , wherein the first liner and the second liner comprise silicon nitride.

15. A method, comprising:
providing a workpiece comprising:
a first epitaxial feature,
a first semiconductor base portion over the first epitaxial feature,
a second epitaxial feature,
a second semiconductor base portion over the second epitaxial feature,
a dielectric fin structure disposed between the first epitaxial feature and the second epitaxial feature, and
an isolation feature disposed over the dielectric fin structure and along sidewalls of the first semiconductor base portion and the second semiconductor base portion;

forming a patterned hard mask over the workpiece, wherein the first semiconductor base portion is exposed in the patterned hard mask;
etching the first semiconductor base portion using the patterned hard mask as an etch mask to expose the first epitaxial feature;
depositing a first nitride liner over the first epitaxial feature and the isolation feature; and
depositing a first dielectric layer over the first nitride liner.

16. The method of claim 15 , wherein the etching comprises recessing the first epitaxial feature.

17. The method of claim 15 , further comprising:
planarizing the workpiece to remove the patterned hard mask such that top surfaces of the first nitride liner, the first dielectric layer, the isolation feature, and the second epitaxial feature are coplanar.

18. The method of claim 17 , further comprising:
recessing the second semiconductor base portion to expose the second epitaxial feature in a backside contact trench;
recessing the exposed second epitaxial feature;
depositing a second nitride liner over the recessed second epitaxial feature and the backside contact trench; and
anisotropically recessing the second nitride liner to expose the second epitaxial feature.

19. The method of claim 18 , further comprising:
forming a silicide feature on the second epitaxial feature; and
depositing a metal material in the backside contact trench to form a backside contact.

20. The method of claim 19 , further comprising:
planarizing the first dielectric layer, the first nitride liner, the second nitride liner, the isolation feature, and the backside contact to form a planar surface;
depositing a second dielectric layer on the planar surface; and
forming a conductive line in the second dielectric layer such that the conductive line is in direct contact with the backside contact.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Su Huan-Chieh
• Yu li-zhen
• Chen Chun-Yuan
• Chiu Shih-Chuan
• Chuang Cheng-Chi
• Lin Yu-Ming
• Wang Chih-Hao

Classifications

• H10P76/2041

  Photolithographic processes · CPC title

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/427

  Power or ground buses · CPC title