Split rail structures located in adjacent metal layers

Patent metadata

Field	Value
Publication number	US-10020261-B2
Application number	US-201615294286-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 14, 2016
Publication date	Jul 10, 2018
Grant date	Jul 10, 2018

Abstract

A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first interconnect layer, the first interconnect layer including:
a plurality of first conductive elements that each extends in a first direction; and
a first rail that extends in the first direction; and

a second interconnect layer different from the first interconnect layer, the second interconnect layer including:
a plurality of second conductive elements that each extends in a second direction, the second direction being different from the first direction, wherein each of the second conductive elements overlaps with three or more of the first conductive elements in a planar view, and wherein each of the first conductive elements overlaps with three or more of the second conductive elements in the planar view; and
a second rail that extends in the first direction, the second rail being physically separated from the second conductive elements, wherein the second rail overlaps with the first rail in the planar view and is electrically coupled to the first rail.

2. The semiconductor device of claim 1 , wherein the second direction is orthogonal to the first direction.

3. The semiconductor device of claim 1 , wherein:
the first interconnect layer is a Mx layer, wherein the Mx layer is a Metal-1 layer or above; and
the second interconnect layer is a Mx+1 layer, wherein the Mx+1 layer is an interconnect layer immediately above the Mx layer.

4. The semiconductor device of claim 1 , further comprising a plurality of conductive vias disposed between the first interconnect layer and the second interconnect layer, wherein the second rail is electrically coupled to the first rail through a subset of the conductive vias.

5. The semiconductor device of claim 1 , wherein:
the first rail has a first dimension that is measured in the second direction;
the second rail has a second dimension that is measured in the second direction; and
the second dimension is smaller than the first dimension.

6. The semiconductor device of claim 5 , wherein:
the first conductive elements each has a third dimension that is measured in the second direction;
the second conductive elements each has a fourth dimension that is measured in the first direction; and
the first dimension and the second dimension are each greater than the third dimension or the fourth dimension.

7. The semiconductor device of claim 1 , wherein the first interconnect layer further includes a third rail that extends parallel to the first rail, and wherein the plurality of first conductive elements is disposed between the first rail and the third rail in the planar view.

8. The semiconductor device of claim 7 , wherein the second interconnect layer further includes a fourth rail that extends parallel to the second rail, and wherein the plurality of second conductive elements is disposed between the second rail and the fourth rail in the planar view.

9. The semiconductor device of claim 1 , wherein the first conductive elements, the first rail, the second conductive elements, and the second rail are parts of a Complementary Metal-Oxide-Semiconductor (CMOS) cell.

10. The semiconductor device of claim 1 , wherein the first rail and the second rail are portions of: a voltage supply rail or a ground rail.

11. A semiconductor device, comprising:
a plurality of circuit cells, wherein each of the circuit cells includes:
a first metal layer, the first metal layer including:
a plurality of first metal lines that each extends along a first axis; and
a first rail structure that extends along the first axis, wherein the first rail structure is physically separated from the first metal lines;

a second metal layer located over the first metal layer, the second metal layer including:
a plurality of second metal lines that each extends along a second axis orthogonal to the first axis, wherein each of the second metal lines overlaps with three or more of the first metal lines in a top view, and wherein each of the first metal lines overlaps with three or more of the second metal lines in top planar view; and
a second rail structure that extends along the first axis, the second rail structure being physically separated from the second metal lines, wherein the second rail structure is located directly over the first rail structure; and

a plurality of vias located between the first metal layer and the second metal layer, wherein a subset of the vias electrically interconnect the first rail structure to the second rail structure.

12. The semiconductor device of claim 11 , wherein:
the first rail structure has a first critical dimension (CD) that is measured along the second axis;
the second rail structure has a second CD that is measured along the second axis;
the first metal lines each have a third CD that is measured along the second axis;
the second metal lines each have a fourth CD that is measured along the first axis;
the second CD is less than the first CD;
the first CD is larger than the third CD; and
the second CD is larger than the fourth CD.

13. The semiconductor device of claim 11 , wherein:
at least one of the circuit cells includes a Complementary Metal-Oxide-Semiconductor (CMOS) cell; and
the first rail structure and the second rail structure are portions of a voltage supply rail or portions of a ground rail of the CMOS cell.

14. The semiconductor device of claim 11 , wherein:
the second metal lines have a minimum pitch that is less than about 54 nanometers; and
the second rail structure is physically separated from the second metal lines by a distance less than about 40 nanometers.

15. A semiconductor device, comprising:
an interconnect structure that includes a plurality of interconnect layers, wherein the interconnect structure includes:
a first interconnect layer, the first interconnect layer including:
a plurality of first conductive elements that each extends in a first direction; and
a first rail that extends in the first direction, wherein the first rail has a first dimension that is measured in a second direction perpendicular to the first direction, and wherein the first rail and the first conductive elements have substantially similar dimensions in the first direction;

a second interconnect layer different from the first interconnect layer, the second interconnect layer including:
a plurality of second conductive elements that each extends in the second direction; and
a second rail that extends in the first direction, the second rail being physically separated from the second conductive elements, wherein the second rail overlaps with the first rail in a planar view and is electrically coupled to the first rail, wherein the second rail has a second dimension that is measured in the second direction, the second dimension being smaller than the first dimension; and

a plurality of conductive vias disposed between the first interconnect layer and the second interconnect layer, wherein the second rail is electrically coupled to the first rail through a subset of the conductive vias.

16. The semiconductor device of claim 15 , wherein no other interconnect layer is disposed between the first interconnect layer and the second interconnect layer.

17. The semiconductor device of claim 15 , wherein:
the first conductive elements each has a third dimension that is measured in the second direction;
the second conductive elements each has a fourth dimension that is measured in the first direction; and
the first dimension and the second dimension are each greater than the third dimension or the fourth dimension.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wu Chia-Tien
• Liu Hsiang-Wei
• Chu Wei-Chen

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P76/40

  of masks comprising inorganic materials · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title