Three-dimensional module with integrated passive components

Patent metadata

Field	Value
Publication number	US-11217542-B2
Application number	US-202016926606-A
Country	US
Kind code	B2
Filing date	Jul 10, 2020
Priority date	Jul 10, 2019
Publication date	Jan 4, 2022
Grant date	Jan 4, 2022

Abstract

A three-dimensional (3-D) module with integrated passive components includes a plurality of vertically stacked sub-modules. Each sub-module comprises a device level comprising a high-k dielectric (e.g. ceramic) material and an interconnect level comprising a low-k dielectric (e.g. organic) material. The passive components in the device level are fired integrally, whereas the device level and the interconnect level are fired independently.

First claim

What is claimed is:

1. A module with integrated passive components, comprising a first capacitor at a first location on a device level and a second capacitor at a second location on said device level, wherein:
said first capacitor comprises a first ceramic body, a pair of first external electrodes, and a plurality of first internal electrodes extending from said first external electrodes into said first ceramic body in a first interleaving manner;
said second capacitor comprise a second ceramic body, a pair of second external electrodes, and a plurality of second internal electrodes extending from said second external electrodes into said second ceramic body in a second interleaving manner;
said first and second ceramic bodies comprise a same ceramic material; said first capacitor has a smaller capacitance value than said second capacitor; said first internal electrodes is smaller in number than said second internal electrodes;
the lower surfaces of said first and second capacitors are co-planar; and, the upper surfaces of said first and second capacitors are co-planar.

2. A module with integrated passive components, comprising a first capacitor at a first location on a device level and a second capacitor at a second location on said device level, wherein:
said first capacitor comprises a first ceramic body with a capacitive portion and a dummy portion, a pair of first external electrodes, and a plurality of first internal electrodes extending from said first external electrodes into said capacitive portion in a first interleaving manner, wherein said dummy portion does not comprise any of said first internal electrodes;
said second capacitor comprise a second ceramic body without any dummy portion, a pair of second external electrodes, and a plurality of second internal electrodes extending from said second external electrodes into said second ceramic body in a second interleaving manner;
said first and second ceramic bodies comprise a same ceramic material; said first capacitor has a smaller capacitance value than said second capacitor;
the lower surfaces of said first and second capacitors are co-planar; and, the upper surfaces of said first and second capacitors are co-planar.

3. A module with integrated passive components, comprising a first capacitor at a first location on a device level and a second capacitor at a second location on said device level, wherein:
said first capacitor comprises a first ceramic body with a capacitive portion and a dummy portion, a pair of first external electrodes, and a plurality of first internal electrodes extending from said first external electrodes into said capacitive portion in a first interleaving manner, wherein said dummy portion does not comprise any of said first internal electrodes;
said second capacitor comprise a second ceramic body without any dummy portion, a pair of second external electrodes, and a plurality of second internal electrodes extending from said second external electrodes into said second ceramic body in a second interleaving manner;
said first and second ceramic bodies comprise a same ceramic material; said first capacitor has a smaller capacitance value than said second capacitor;
each of said first internal electrodes is co-planar with a selected one of said second internal electrodes.

Assignees

• Univ Southern Sci & Tech

Inventors

• Zhang Guobiao
• Yu Hongyu
• Guo Yuejin
• Zhou Shengming
• Zhang Guoxing
• Liu Guangzhao
• Hu Mingtao
• Zhang Wang

Classifications

• H10P72/7436

  used to support a device or a wafer when forming electrical connections thereto · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title