Multilayer ceramic capacitor and mounting board for multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-9646770-B2
Application number	US-201615042563-A
Country	US
Kind code	B2
Filing date	Feb 12, 2016
Priority date	Mar 29, 2013
Publication date	May 9, 2017
Grant date	May 9, 2017

Abstract

There is provided multilayer ceramic capacitor including, a ceramic body including a plurality of dielectric layers laminated therein, an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, with the dielectric layers interposed therebetween, and having capacitance formed therein, an upper cover layer formed on an upper portion of the active layer, a lower cover layer formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer, first and second dummy electrode terminals provided in the lower cover layer to be alternately exposed through both end surfaces of the lower cover layer, and first and second external electrodes covering the both end surfaces of the ceramic body.

First claim

What is claimed is:

1. A multilayer ceramic capacitor, comprising:
a ceramic body including a plurality of dielectric layers laminated therein;
an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, with the dielectric layers interposed therebetween, and having capacitance formed therein;
an upper cover layer formed on an upper portion of the active layer;
a lower cover layer formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer;
first and second dummy electrode terminals provided in the lower cover layer to be alternately exposed through both end surfaces of the lower cover layer; and
first and second external electrodes covering the both end surfaces of the ceramic body,
wherein the first and second dummy electrode terminals respectively include a plurality of first and second dummy patterns exposed through the same end surface of the lower cover layer, with the dielectric layers interposed therebetween, and
when an interval between the first and second internal electrodes is defined as Ta and an interval between the first and second dummy electrode terminals is defined as Tb, Tb≧Ta is satisfied.

2. The multilayer ceramic capacitor of claim 1 , wherein when half of an overall thickness of the ceramic body is denoted by A, a thickness of the lower cover layer is denoted by B, half of an overall thickness of the active layer is denoted by C, and a thickness of the upper cover layer is denoted by D, a ratio of deviation of a central portion of the active layer from a central portion of the ceramic body, (B+C)/A, satisfies 1.063≦(B+C)/A≦1.745.

3. The multilayer ceramic capacitor of claim 1 , wherein a ratio of the thickness D of the upper cover layer to the thickness B of the lower cover layer, D/B, satisfies 0.021≦D/B≦0.422.

4. The multilayer ceramic capacitor of claim 1 , wherein a ratio of the thickness B of the lower cover layer to half A of the overall thickness of the ceramic body, B/A, satisfies 0.329≦B/A≦1.522.

5. The multilayer ceramic capacitor of claim 1 , wherein a ratio of half C of the overall thickness of the active layer to the thickness B of the lower cover layer, C/B, satisfies 0.146≦C/B≦2.458.

6. The multilayer ceramic capacitor of claim 1 , wherein a point of inflection formed on the both end surfaces of the ceramic body is formed at a height equal to or lower than that of a center of the overall thickness of the ceramic body, due to a difference between a deformation rate occurring in the central portion of the active layer and a deformation rate occurring in the lower cover layer when a voltage is applied thereto.

7. The multilayer ceramic capacitor of claim 1 , wherein the upper cover layer is devoid of dummy electrode terminals.

8. A mounting board for a multilayer ceramic capacitor, comprising:
a printed circuit board having first and second electrode pads disposed thereon; and
a multilayer ceramic capacitor mounted on the printed circuit board,
wherein the multilayer ceramic capacitor includes: a ceramic body including a plurality of dielectric layers laminated therein; an active layer including a plurality of first and second internal electrodes alternately exposed through both end surfaces of the ceramic body, with the dielectric layers interposed therebetween; an upper cover layer formed on an upper portion of the active layer; a lower cover layer formed on a lower portion of the active layer and having a thickness greater than that of the upper cover layer; first and second dummy electrode terminals provided in the lower cover layer to be alternately exposed through both end surfaces of the lower cover layer; and first and second external electrodes formed from the both end surfaces of the ceramic body to upper and lower surfaces thereof to be electrically connected to exposed portions of the first and second internal electrodes and the first and second dummy electrode terminals, respectively, and to be connected to the first and second electrode pads, respectively, through a soldering,
the first and second dummy electrode terminals respectively include a plurality of first and second dummy patterns exposed through the same end surface of the lower cover layer, with the dielectric layers interposed therebetween, and
when an interval between the first and second internal electrodes is defined as Ta and an interval between the first and second dummy electrode terminals is defined as Tb, Tb≧Ta is satisfied.

9. The mounting board for a multilayer ceramic capacitor of claim 8 , wherein in the multilayer ceramic capacitor, when half of an overall thickness of the ceramic body is denoted by A, a thickness of the lower cover layer is denoted by B, half of an overall thickness of the active layer is denoted by C, and a thickness of the upper cover layer is denoted by D, a ratio of deviation of a central portion of the active layer from a central portion of the ceramic body, (B+C)/A, satisfies 1.063≦(B+C)/A≦1.745.

10. The mounting board for a multilayer ceramic capacitor of claim 8 , wherein in the multilayer ceramic capacitor, a ratio of the thickness D of the upper cover layer to the thickness B of the lower cover layer, D/B, satisfies 0.021≦D/B≦0.422.

11. The mounting board for a multilayer ceramic capacitor of claim 8 , wherein in the multilayer ceramic capacitor, a ratio of the thickness B of the lower cover layer to half A of the overall thickness of the ceramic body, B/A, satisfies 0.329≦B/A≦1.522.

12. The mounting board for a multilayer ceramic capacitor of claim 8 , wherein in the multilayer ceramic capacitor, a ratio of half C of the overall thickness of the active layer to the thickness B of the lower cover layer, C/B, satisfies 0.146≦C/B≦2.458.

13. The mounting board for a multilayer ceramic capacitor of claim 8 , wherein in the multilayer ceramic capacitor, a point of inflection formed on the both end surfaces of the ceramic body is formed at a height equal to or lower than that of the soldering, due to a difference between a deformation rate occurring in the central portion of the active layer and a deformation rate occurring in the lower cover layer when a voltage is applied thereto.

14. The mounting board for a multilayer ceramic capacitor of claim 8 , wherein the upper cover layer is devoid of dummy electrode terminals.

Assignees

• Samsung Electro Mech

Inventors

• Ahn Young Ghyu
• Park Sang Soo
• Park Min Cheol
• Lee Byoung Hwa

Classifications

• H01G4/224

  Housing; Encapsulation · CPC title

• H05K2201/10015

  Non-printed capacitor · CPC title

• H01G4/12 Primary

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H05K1/181

  associated with surface mounted components · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title