Apparatus and methods including source gates

Patent metadata

Field	Value
Publication number	US-11211126-B2
Application number	US-202017027425-A
Country	US
Kind code	B2
Filing date	Sep 21, 2020
Priority date	Aug 15, 2011
Publication date	Dec 28, 2021
Grant date	Dec 28, 2021

Abstract

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

First claim

What is claimed is:

1. A memory device, comprising:
multiple blocks of strings of memory cells, each string of memory cells comprising multiple charge storage devices associated with a respective semiconductor channel material, wherein the multiple strings of memory cells within respective blocks of memory cell strings are arranged in rows and columns, each of the multiple strings coupled to a common source through both a source gate and a source select gate, wherein the multiple blocks of memory cell strings each include respective sub-blocks of memory cell strings;
wherein each source gate of the multiple memory cell strings in a block includes a respective control gate, wherein the multiple control gates of the source gates of the block are coupled together to be controlled in common; and
wherein each source select gate (SGS) of the multiple strings in a respective sub-block of the multiple strings includes a respective control gate, and wherein the control gates of the multiple SGSs within respective sub-blocks are coupled together to be controlled in common, wherein the multiple strings within each sub-block are less than all of the multiple strings of the respective block.

2. The memory device of claim 1 , further comprising multiple drain select gates (SGDs), each SGD associated with a respective string of the multiple strings of charge storage devices, each SGD having a control gate, and
wherein the control gates of the SGDs associated with multiple memory cell strings within individual sub-blocks of memory cell strings are coupled to one another to be controlled in common.

3. The memory device of claim 2 , wherein the memory device is configured to perform a read operation on a selected memory cell within a first sub-block of multiple strings of memory cells, the first sub-block within a first block of memory cell strings through operations comprising,
biasing the common source to a first voltage;
controlling the source gates within the first block to an “on” state with a first voltage; and
controlling the SGSs of the first sub-block containing the selected memory cell to an “on” state with a second voltage, while controlling SGSs of additional sub-blocks within the first block to an “off” state with a third voltage.

4. The memory device of claim 3 , wherein the operations for performing the read operation further comprise:
applying a fourth conductive voltage to multiple access lines in the first block associated with non-selected memory cells; and
sequentially applying multiple read voltages to an access line in the first block associated with the selected memory cell.

5. The memory device of claim 4 , wherein the operations for performing the read operation further comprise controlling the SGDs in the first sub-block to an “on” state with a fifth voltage; and
controlling the SGDs of other sub-blocks within the first block to an “off” state with a sixth of voltage.

6. The memory device of claim 3 , wherein the first voltage applied to the source gates of the first block is greater than the second voltage applied to the source select gates (SGSs) of the first sub-block.

7. The memory device of claim 5 , wherein the second voltage applied to control the SGSs of the first sub-block to an “on” state is the same as the fifth voltage applied to control the SGDs in the first sub-block to an “on” state.

8. The memory device of claim 1 , wherein each source gate at least partially surrounds the semiconductor channel material of the string of charge storage devices with which the source gate is associated.

9. The memory device of claim 1 , wherein each source select gate at least partially surrounds the semiconductor channel material of the string of charge storage devices with which the source select gate is associated.

10. The memory device of claim 1 , wherein each source select gate is between multiple charge storage devices of the respective string and the source gate associated with the respective string.

11. The memory device of claim 1 , wherein a first sub-block comprises only strings in a single column of the block.

12. The memory device of claim 11 , wherein a first sub-block comprises all strings in a single column of the block.

13. The memory device of claim 1 , wherein each block of memory cell strings comprises four sub-blocks of memory cell strings.

14. The memory device of claim 1 , wherein each string of memory cells extends vertically, with each charge storage device of the memory cells in a string formed in a respective tier of multiple vertically arranged tiers, and wherein each charge storage device includes a gate; and
wherein each tier comprises a respective access line, wherein each access line is coupled to gates of multiple charge storage devices in the respective tier, including a single charge storage device gate from each of multiple memory cell strings within the block.

15. A method of operating memory device, comprising:
a block of vertical strings of memory cells, each string of memory cells comprising multiple charge storage devices connected in series and associated with a respective semiconductor channel material, each of the multiple strings coupled to a common source through both a source gate and a source select gate (SGS), wherein each of the multiple strings is coupled to a respective data line through a select gate drain (SGD), and wherein the multiple blocks of memory cell strings each include respective sub-blocks of memory cell strings;
wherein each source gate of the multiple memory cell strings in a block includes a respective control gate, wherein multiple control gates of the source gates of the block are coupled together to be controlled in common;
wherein each SGS of a respective sub-block of the multiple strings includes a respective control gate, and wherein the multiple control gates of the SGSs within respective sub-blocks are coupled together to be controlled in common, wherein the multiple strings within each sub-block are less than all of the multiple strings of the respective block; and
wherein the method comprises:
performing a read operation on a selected memory cell within a first sub-block of multiple strings of charge storage devices within the block through operations comprising,
biasing the common source to a first voltage;
controlling the source gates within the first block to an “on” state with a first voltage; and
controlling the SGSs of the first sub-block containing the selected memory cell to an “on” state with a second voltage, while controlling SGSs of additional sub-blocks within the first block to an “off” state with a third voltage;
controlling the SGDs in the first sub-block to an “on” state with a fourth voltage; and
controlling the SGDs of other sub-blocks within the block to an “off” state with a fifth voltage.

16. The method of claim 15 , further comprising:
applying a sixth conductive voltage to multiple access lines in the block associated with non-selected memory cells; and
sequentially applying multiple read voltages to an access line in the block associated with the selected memory cell.

17. The method of claim 16 , wherein the first voltage applied to the source gates of the first block is greater than the second voltage applied to the (SGSs) of the first sub-block.

18. The method of claim 17 , wherein the second voltage applied to control the SGSs of the first sub-block to an “on” state is the same as the fifth voltage applied to control the SGDs in the first sub-block to an “on” state.

19. The method of claim 15 , wherein

Assignees

• Micron Technology Inc

Inventors

• Goda Akira
• Ahmed Shafqat
• Hasnat Khaled
• Parat Krishna K

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title