Partial page memory operations

Patent metadata

Field	Value
Publication number	US-9653171-B2
Application number	US-201615131719-A
Country	US
Kind code	B2
Filing date	Apr 18, 2016
Priority date	Oct 26, 2012
Publication date	May 16, 2017
Grant date	May 16, 2017

Abstract

Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

First claim

What is claimed is:

1. An apparatus comprising:
a plurality of strings of memory cells, the memory cells formed in a plurality of tiers, the strings of memory cells arrange in memory blocks, wherein a memory block among the memory block includes a first partial block and a second partial block, the first partial block including first memory cells in a first tier of the plurality of tiers, the second partial block including second memory cells in the first tier of the plurality of tiers;
global access lines, each of the global access lines shared by memory cells in a respective tier of the plurality of tiers;
a first local access line shared by the first memory cells, the first local access line coupled to a global access line of the global access lines through a first string driver; and
a second local access line shared by the second memory cells, the second local access line coupled to the global access line through a second string driver.

2. The apparatus of claim 1 , further comprising a global drain select line, wherein the first partial block includes first strings of memory cells of the plurality of strings of memory cells, the second partial block includes second strings of memory cells of the plurality of strings of memory cells, the first strings of memory cells share a first local drain select line, the second strings of memory cells share a second local drain select line, the first local drain select line is coupled to the global drain select line through a first select line driver, and the second local drain select line is coupled to the global drain select line through a second select line driver.

3. The apparatus of claim 1 , further comprising a global source select line, wherein the first partial block includes first strings of memory cells of the plurality of strings of memory cells, the second partial block includes second strings of memory cells of the plurality of strings of memory cells, the first strings of memory cells share a first local source select line, the second strings of memory cells share a second local source select line, the first local source select line is coupled to the global source select line through a first select line driver, and the second local source select line is coupled to the global source select line through a second select line driver.

4. The apparatus of claim 1 , further comprising a third local access line coupled to the global access line through a third second string driver, wherein the memory block includes a third partial block, the third partial block including third memory cells in the first tier of the plurality of tiers, and the third memory cells sharing the third local access line.

5. The apparatus of claim 1 , wherein the first memory cells are configured to store first data, and the second memory cells are configured to store second data after the first data is stored.

6. The apparatus of claim 1 , wherein the first data is included in a first partial page of a page, and the second data is included in a second partial page of the page.

7. The apparatus of claim 1 , wherein the first memory cells are included in a first tile, the second memory cells are included in a second tile, and the first and second title are proximately related according to a numerical address sequence.

8. The apparatus of claim 1 , wherein the first memory cells are included in a first tile, the second memory cells are included in a second tile, and the first and second title are proximately un related according to a numerical address sequence.

9. An apparatus comprising:
a plurality of strings of memory cells, the memory cells formed in a plurality of tiers, the strings of memory cells arrange in memory blocks, wherein a memory block among the memory block includes a first partial block and a second partial block, the first partial block including first strings of memory cells of the plurality of strings of memory cells, the first strings of memory cells including first memory cells in a first tier of the plurality of tiers, the first memory cells mapped to a first partial page of a page, the second partial block including second strings of memory cells of the plurality of strings of memory cells, the second strings of memory cells including second memory cells in the first tier of the plurality of tiers, the second memory cells mapped to a second partial page of the page;
first data lines coupled to the first strings of memory cells; and
second data lines different from the first data lines, the second data lines coupled to the second strings of memory cells.

10. The apparatus of claim 9 , further comprising:
global access lines, each of the global access lines shared by memory cells in a respective tier of the plurality of tiers;
a first local access lines shared by the first memory cells, the first local access line coupled to a global access line of the global access lines through a first string driver; and
a second local access lines shared by the second memory cells, the second local access line coupled to the global access line through a second string driver.

11. The apparatus of claim 10 , further comprising a global drain select line, wherein the first partial block includes first strings of memory cells of the plurality of strings of memory cells, the second partial block includes second strings of memory cells of the plurality of strings of memory cells, the first strings of memory cells share a first local drain select line, the second strings of memory cells share a second local drain select line, the first local drain select line is coupled to the global drain select line through a first select line driver, and the second local drain select line is coupled to the global drain select line through a second select line driver.

12. The apparatus of claim 11 , further comprising a global source select line, wherein the first partial block includes first strings of memory cells of the plurality of strings of memory cells, the second partial block includes second strings of memory cells of the plurality of strings of memory cells, the first strings of memory cells share a first local source select line, the second strings of memory cells share a second local source select line, the first local source select line is coupled to the global source select line through a first select line driver, and the second local source select line is coupled to the global source select line through a second select line driver.

13. The apparatus of claim 9 , further comprising third data lines, wherein the memory block includes a third partial block, the third partial block including third strings of memory cells of the plurality of strings of memory cells, the third strings of memory cells including third memory cells in the first tier of the plurality of tiers, the third memory cells mapped to a third partial page of the page, and the third data lines coupled to the third strings of memory cells.

14. The apparatus of claim 13 , further comprising a control unit to activate the first data lines during a memory operation and disable the second data lines in the memory operation.

15. The apparatus of claim 14 , wherein the control unit is configured to store a first portion of data in the first memory cells at a first time, and to store a second portion of the data in the second memory cells at a second time after the first time.

16. A method comprising:
receiving first data;
storing the first data in a first partial page of a memory device; and
receiving second data;
storing the second data in a second partial page of the page after the first data is stored in the first

Assignees

• Micron Technology Inc

Inventors

• Abraham Michael
• Tanaka Tomoharu
• Kawai Koichi
• Einaga Yuichi

Classifications

• G11C16/107 Primary

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title