Apparatus and methods including source gates

Patent metadata

Field	Value
Publication number	US-9779816-B2
Application number	US-201615166029-A
Country	US
Kind code	B2
Filing date	May 26, 2016
Priority date	Aug 15, 2011
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

First claim

What is claimed is:

1. An apparatus comprising:
a first string of charge storage devices associated with a pillar comprising semiconductor material;
a second string of charge storage devices associated with a pillar comprising semiconductor material;
a first source select device having a gate, the first source select device coupled to the first string of charge storage devices;
a second source select device having a gate, the second source select device coupled to the second string of charge storage devices, wherein the gates of the first and second source select devices are separated from one another;
a first source gate device having a gate, the first source gate device coupled between the first source select device and a source; and
a second source gate device having a gate, the second source gate device coupled between the second source select device and the source, wherein the gates of the first and second source gate devices are coupled to one another to be controlled in common.

2. The apparatus of claim 1 , comprising:
a third string of charge storage devices associated with a pillar comprising semiconductor material;
a fourth string of charge storage devices associated with a pillar comprising semiconductor material;
a third source select device having a gate, the third source select device coupled to the third string of charge storage devices;
a fourth source select device having a gate, the fourth source select device coupled to the fourth string of charge storage devices, wherein the gates of the third and fourth source select devices are separated from each other;
a third source gate device having a gate, the third source gate device coupled between the third source select device and the source; and
a fourth source gate device having a gate, the fourth source gate device coupled between the fourth source select device and the source; and

wherein the gates of the first, second, third, and fourth source gate devices are coupled to one another to be controlled in common.

3. The apparatus of claim 2 , wherein:
gates of the first and third source select devices are coupled to each other to be controlled in common; and
gates of the second and fourth source select devices are coupled to each other to be controlled in common.

4. The apparatus of claim 3 , further comprising:
a first drain select device having a gate, the first drain select device coupled to the first string of charge storage device;
a second drain select device having a gate, the second drain select device coupled to the second string of charge storage devices;
a third drain select device having a gate, the third drain select device coupled to the third string of charge storage devices; and
a fourth drain select device having a gate, the fourth drain select device coupled to the fourth string of charge storage devices:
wherein gates of the first and second drain select devices are separated from each other,
wherein gates of the first and third drain select devices are coupled to each other to be controlled in common, and
wherein gates of the second and fourth drain select devices are coupled to each other to be controlled in common.

5. The apparatus of claim 1 , wherein the first string of the charge storage devices comprises a floating gate transistor.

6. The apparatus of claim 1 , wherein the second string of the charge storage devices comprises a charge trap transistor.

7. The apparatus of claim 1 , wherein the pillar extends from a data line to a well in a substrate.

8. The apparatus of claim 1 , wherein a distance between two gates of the charge storage devices associated with a pillar is shorter than a distance between the gate of the first source select device and the gate of the first source gate device.

9. The apparatus of claim 1 , comprising:
a first block of memory cells comprising,
the first string of charge storage devices,
the second string of charge storage devices,
the first source select device,
the second source select device,
the first source gate device, and
the second source gate device.

10. The apparatus of claim 9 , comprising:
a second block of memory cells, comprising,
a third string of charge storage devices associated with a pillar comprising semiconductor material;
a fourth string of charge storage devices associated with a pillar comprising semiconductor material;
a third source select device having a gate, the third source select device coupled to the third string of charge storage devices;
a fourth source select device having a gate, the fourth source select device coupled to the fourth string of charge storage devices, wherein the gates of the third and fourth source select devices are separated from the gates of the first and second source select devices;
a third source gate device having a gate, the third source gate device coupled between the third source select device and a second source; and
a fourth source gate device having a gate, the fourth source gate device coupled between the fourth source select device and the source, wherein the gates of the first, second, third and fourth source gate devices are coupled to each other to be controlled in common.

11. An apparatus, comprising:
multiple strings comprising charge storage devices;
a first unit of source select devices respectively coupled to strings of a first group of strings of the multiple strings to control conduction between the strings of the first group and a source;
a second unit of source select devices respectively coupled to strings of a second group of strings of the multiple strings to control conduction between the strings of the second group and the source, the first group of strings being different from the second group of strings; and
a first unit of source gate devices, each respectively coupled in series with a source select device of the first and second units of source select devices, to control conduction between the strings of the first and second groups of strings and the source.

12. The apparatus of claim 11 , comprising
a first unit of drain select devices, each coupled to a respective string of the first group of strings, to control conduction between the string and a first data line region; and
a second unit of drain select devices, each coupled to a respective string of the second group of strings, to control conduction between the string and a second data line region.

13. The apparatus of claim 11 , wherein the devices of the third unit of source gate devices are coupled to strings in a block.

14. The apparatus of claim 13 , wherein the first unit of source select devices is coupled to strings of a first sub-block and the second unit of source select devices is coupled to strings of a second sub-block.

15. The apparatus of claim 11 , wherein a distance between two gates of charge storage devices associated with one string is shorter than a distance between a gate of one source select device associated with the first unit of source select devices and a gate of one source gate device associated with the third unit of source gate devices.

16. The apparatus of claim 11 , wherein the charge storage devices comprise floating gate transistors.

17. The apparatus of claim 11 , wherein the charge storage devices comprise charge trap transistors.

18. An apparatus comprising:
a memory unit including:
multiple strings of charge storage devices connected by a channel, strings arranged in multiple rows,
each string associated with a pillar comprising semiconductor material; and
each string in a row includin

Assignees

• Micron Technology Inc

Inventors

• Goda Akira
• Ahmed Shafqat
• Hasnat Khaled
• Parat Krishna K

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/0408

  comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence) · CPC title