Apparatus and methods including source gates

Patent metadata

Field	Value
Publication number	US-10170189-B2
Application number	US-201715721007-A
Country	US
Kind code	B2
Filing date	Sep 29, 2017
Priority date	Aug 15, 2011
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

First claim

What is claimed is:

1. A memory array, comprising:
multiple strings of charge storage devices, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns, each of the multiple strings coupled to a common source through both a source gate device and a source select gate device;
wherein each source gate device includes a gate, and is configured to partially control conduction between the pillar of the respective string and the common source, wherein each source select gate device includes a gate and is also configured to partially control conduction between the pillar of the respective string and the common source,
wherein the gates of the source gate devices associated with each of the multiple strings of charge storage devices are coupled together to be controlled in common; and

wherein the gates of source select gate devices associated with a first group of strings of the multiple strings of charge storage devices are coupled together to be controlled in common, wherein the first group of strings is less than all of the multiple strings of charge storage devices.

2. The memory array of claim 1 , further comprising multiple drain select gate devices,
each drain select gate associated with a respective string of the multiple strings of charge storage devices,
each drain select gate device having a gate, and
wherein the gates of the drain select gate devices associated with the first group of strings are coupled to one another to be controlled in common.

3. The memory array of claim 1 , wherein each source gate device at least partially surrounds the pillar of the string of charge storage devices with which the source gate device is associated.

4. The memory array of claim 1 , wherein each source select gate device at least partially surrounds the pillar of the string of charge storage devices with which the source select gate device is associated.

5. The memory array of claim 1 , wherein each source select gate device is between the plurality of string of charge storage devices associated with a respective pillar and the source gate device associated with such respective pillar.

6. The memory array of claim 1 , wherein the multiple strings of charge storage devices comprises all strings of charge storage devices in a block of memory.

7. The memory array of claim 1 , wherein the first group of strings of charge storage devices comprises the strings in a sub-block of the memory array.

8. The memory array of claim 1 , wherein the first group of strings of charge storage devices comprises only strings in a single column of the memory array.

9. The memory array of claim 8 , wherein the first group of strings of charge storage devices comprises all strings in a single column of the memory array of the memory array.

10. A memory device, comprising:
multiple strings of charge storage devices in a block of memory, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns in the block of memory;
multiple drain select gate devices, each drain select gate device at least partially surrounding a respective pillar of one of the multiple strings of charge storage devices,
wherein the drain select gate device is between the string of charge storage devices associated with the pillar and a respective data line, and
wherein the gates of drain select gate devices associated with a first group of strings are coupled to one another to be controlled in common;

multiple source gate devices, each source gate at least partially surrounding a respective pillar of one of the multiple strings, each source gate device coupled to a source and configured to partially control conduction between the pillar and the source,
wherein each source gate device includes a gate,
wherein the gate of each source gate device is coupled to the gates of multiple additional source gate devices associated with a second group of strings of charge storage devices, wherein the first group of strings is a subset of the second group of strings; and
wherein the second group of strings includes a source gate device of a string in the same row, and further includes the gate of a source gate device in another row, to be controlled in common; and

multiple source select gate devices, each source select gate device at least partially surrounding a respective pillar of one of the multiple strings,
wherein each source select gate device is between the plurality of string of charge storage devices associated with the pillar and the source gate device, and is configured to partially control conduction between the pillar and the source, and
wherein the source select gate devices associated with the first group of strings are coupled to one another to be controlled in common.

11. The memory device of claim 10 , wherein the second group of strings comprises all strings in the block of memory.

12. The memory device of claim 10 , wherein the first group of strings of charge storage devices comprises the strings in a sub-block of the memory array.

13. The memory device of claim 10 , wherein the first group of strings comprises strings in a single column in the block of memory.

14. The memory device of claim 13 , wherein the first group of strings comprises all strings in a single column in the block of memory.

15. The memory device of claim 10 , wherein each string of charge storage devices extends vertically, with each charge storage device in a string formed in a respective tier of multiple vertically arranged tiers, and wherein each charge storage device includes a gate; and
wherein each tier comprises a respective access line, wherein each access line is coupled to gates of multiple charge storage devices in the respective tier, including a single charge storage device gate from each of multiple memory cell strings.

16. A method for operating a memory array, wherein the memory array comprises:
multiple strings of charge storage devices, each string comprising multiple charge storage devices associated with a respective pillar comprising semiconductor material, wherein the multiple strings of charge storage devices are arranged in rows and columns, each of the multiple strings coupled to a common source through both of a source gate device and a source select gate device;
wherein each source gate device includes a gate, and is configured to partially control conduction between the pillar of the respective string and the common source,
wherein each source select gate device includes a gate and is configured to partially control conduction between the pillar of the respective string and the common source,
wherein the gates of the source gate devices associated with each of the multiple strings of charge storage devices are coupled together to be controlled in common,
wherein the gates of source select gate devices associated with a first group of strings of the multiple strings of charge storage devices are coupled together to be controlled in common,
wherein the first group of strings is less than all of the multiple strings of charge storage devices; and
wherein the multiple charge storage devices each includes a respective gate, and

wherein the gates of individual respective charge storage devices, one from each string of a second group of strings of the multiple strings of charge storage devices, are coupled to a respective acce

Assignees

• Micron Technology Inc

Inventors

• Goda Akira
• Ahmed Shafqat
• Hasnat Khaled
• Parat Krishna K

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/12

  Programming voltage switching circuits · CPC title