Methods and apparatuses including a string of memory cells having a first select transistor coupled to a second select transistor

Patent metadata

Field	Value
Publication number	US-9318200-B2
Application number	US-201414456222-A
Country	US
Kind code	B2
Filing date	Aug 11, 2014
Priority date	Aug 11, 2014
Publication date	Apr 19, 2016
Grant date	Apr 19, 2016

Abstract

Generally discussed herein are apparatuses and methods. One such apparatus includes a data line, a first memory cell and a first select transistor. The first transistor has a gate and is coupled between the data line and the first memory cell. The apparatus can include a second memory cell and a second select transistor having a gate. The apparatus can include a third select transistor having a gate. The second select transistor is coupled between the second memory cell and the third select transistor. The third select transistor is coupled between the second select transistor and a source. The apparatus can include a drive transistor coupled to both the gate of the first select transistor and the gate of the second select transistor or the gate of the third select transistor.

First claim

What is claimed is:

1. An apparatus comprising:
a data line;
a first memory cell;
a first select transistor having a gate and being coupled between the data line and the first memory cell;
a second memory cell;
a second select transistor having a gate;
a third select transistor having a gate, wherein the second select transistor is coupled between the second memory cell and the third select transistor, and wherein the third select transistor is coupled between the second select transistor and a source; and
a drive transistor having a drain coupled to both:
the gate of the first select transistor; and
the gate of the second select transistor or the gate of the third select transistor.

2. The apparatus of claim 1 , wherein the drive transistor is coupled to the gate of the second select transistor.

3. The apparatus of claim 2 , wherein the drive transistor comprises a first drive transistor, the apparatus further comprising a second drive transistor coupled to the gate of the third select transistor.

4. The apparatus of claim 1 , wherein the drive transistor is coupled to the gate of the third select transistor.

5. The apparatus of claim 4 , wherein the drive transistor comprises a first drive transistor, the apparatus further comprising a second drive transistor coupled to the gate of the second select transistor.

6. The apparatus of claim 1 , further comprising a fourth select transistor coupled between the first select transistor and the first memory cell.

7. The apparatus of claim 1 , wherein the first select transistor, the second select transistor, the third select transistor, and the first and second memory cells are arranged in a U-shaped configuration.

8. The apparatus of claim 7 , further comprising a connection between a control gate of the first and second memory cells.

9. The apparatus of claim 1 , wherein the first select transistor, the second select transistor, the third select transistor, and the first and second memory cells are arranged in a vertical string configuration.

10. The apparatus of claim 1 , wherein the drive transistor is a first drive transistor, and the apparatus further comprises:
a fourth select transistor having a gate and coupled between the data line and the first select transistor; and
a second drive transistor coupled to the gate of the fourth select transistor.

11. The apparatus of claim 1 , further comprising a pass transistor coupled between the first memory cell and the second memory cell.

12. An apparatus comprising:
a plurality of data lines;
a source; and
a plurality of strings of memory cells, each string of the plurality of strings of memory cells including:
a first select transistor coupled to a data line of the plurality of data lines;
a plurality of serially coupled memory cells, the serially coupled memory cells including a first memory cell at a first end thereof and a second memory cell at a second end thereof, the first select transistor coupled between the first memory cell and a respective data line of the plurality of data lines;
a second select transistor coupled between the second memory cell and the source;
a third select transistor coupled between the second select transistor and the source; and

a drive transistor having a drain coupled to both:
the gate of the first select transistor; and
the gate of the second select transistor or the gate of the third select transistor.

13. A method of performing a read operation comprising:
precharging channels of strings of memory cells to a precharge voltage;
driving gates of a plurality of select transistors of an unselected string of memory cells with a single drive transistor to cut-off the channel of the unselected string of memory cells;
driving a gate of a selected memory cell of a selected string of memory cells to a read voltage; and
determining a stored data value of the selected memory cell based on a signal on a data line.

14. The method of claim 13 , further comprising:
driving a gate of an unselected memory cell of the selected string of memory cells to a voltage greater than the read voltage.

15. The method of claim 14 , further comprising:
driving a source to a reference voltage less than the read voltage.

16. The method of claim 14 , further comprising:
driving gates of a plurality of select transistors of the selected string to activate the plurality of select transistors of the selected string in response to the gate of the selected memory cell being driven to the read voltage.

17. The method of claim 14 , further comprising driving the gate of the unselected memory cell of the selected string of memory cells to V cc and then driving the gate of the unselected memory cell of the selected string of memory cells to V ss before driving the gate of the unselected memory cell of the selected string of memory cells to the voltage greater than the read voltage.

18. The method of claim 14 , further comprising driving the gate of the selected memory cell to a voltage greater than the read voltage before driving the gate of the selected memory cell of the selected string of memory cells to the read voltage; and
wherein driving the gate of the unselected memory cell of the selected string of memory cells to a voltage greater than the read voltage includes driving the gate of the unselected memory cell of to the voltage greater than the read voltage concurrently with driving the gate of the selected memory to the voltage greater than the read voltage.

19. A method of performing a program operation comprising:
precharging channels of strings of memory cells to at voltage selected from the group comprising at least of a program enable voltage and a program inhibit voltage;
driving gates of a plurality of select transistors of an unselected string of memory cells with a single drive transistor to cut-off the channel of the unselected string of memory cells; and
driving a gate of a selected memory cell of a selected string of memory cells to a program voltage to program the selected memory cell.

20. The method of claim 19 , further comprising:
driving a gate of an unselected memory cell of the selected string of memory cells to a pass voltage less than the program voltage.

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C5/144

  Detection of predetermined disconnection or reduction of power supply, e.g. power down or power standby · CPC title