Shielded vertically stacked data line architecture for memory

Patent metadata

Field	Value
Publication number	US-2016019970-A1
Application number	US-201514867948-A
Country	US
Kind code	A1
Filing date	Sep 28, 2015
Priority date	Jun 17, 2013
Publication date	Jan 21, 2016
Grant date	—

Abstract

Apparatuses and methods are disclosed, including an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.

First claim

What is claimed is:

1 . A method comprising:
applying a pass voltage to unselected access lines of a plurality of access lines; applying an operational voltage to selected access lines of the plurality of access lines to enable particular memory cells; enabling first shield transistors that couple first alternating data lines of a plurality of vertically stacked data lines to a shield voltage line; and disabling second shield transistors that couple second alternating data lines of the plurality of vertically stacked data lines to the shield voltage line, wherein strings of memory cells comprising the enabled memory cells are operably coupled to the second alternating data lines and strings of memory cells that do not comprise the enabled memory cells are operably coupled to the first alternating data lines.

2 . The method of claim 1 , wherein the operational voltage is a sense voltage.

3 . The method of claim 2 , wherein the shield voltage line is at ground.

4 . The method of claim 3 , further comprising enabling select gate drain and select gate source transistors that are coupled to strings of memory cells comprising the enabled memory cells.

5 . The method of claim 4 , further comprising enabling sense transistors to latch data from selected memory cells into page buffers.

6 . The method of claim 1 , further comprising disabling select gate drain and select gate source transistors that are coupled to strings of memory cells that do not comprise the enabled memory cells.

7 . The method of claim 1 , wherein the operational voltage is a program voltage.

8 . The method of claim 1 , further comprising applying a ground voltage to the shield voltage line when the operational voltage is a sense voltage.

9 . The method of claim 1 , further comprising applying a positive voltage to the shield voltage line when the operational voltage is a program voltage.

10 . A method comprising:
applying a read voltage to selected access lines of a plurality of access lines to enable particular memory cells; applying a read pass voltage to unselected access lines of the plurality of access lines; applying a pre-charge voltage to first alternating data lines of a plurality of vertically stacked data lines; applying a shield voltage to second alternating data lines of the plurality of vertically stacked data lines; applying an enable voltage to select gate drain transistors that couple first memory cell strings, comprising the enabled memory cells, to the first alternating data lines; and applying a disable voltage to select gate drain transistors that couple second memory cell strings that do not comprise the enabled memory cells.

11 . The method of claim 10 , wherein the first alternating data lines are even data lines that are coupled to even data line shield transistors, the method further comprising applying a disable voltage to control gates of the even data line shield transistors such that the even data lines are not operably coupled to a shield voltage line.

12 . The method of claim 11 , wherein the second alternating data lines are odd data lines that are coupled to odd data line shield transistors, the method further comprising applying an enable voltage to control gates of the odd data line shield transistors such that the odd data lines are coupled to the shield voltage line.

13 . The method of claim 12 , further comprising applying an enable voltage to sense transistors that are coupled to the even data lines.

14 . The method of claim 13 , further comprising latching sensed data from the even data lines into page buffers.

15 . A method comprising:
applying a programming voltage to a selected access line of a plurality of access lines to program a selected memory cell in a first string of memory cells; applying a program pass voltage to unselected access lines of the plurality of access lines to disable unselected memory cells; applying page buffer data to a first data line, of a plurality of vertically stacked alternating data lines, operably coupled to the first string of memory cells; applying a shield voltage to adjacent data lines, of the plurality of vertically stacked alternating data lines, that are adjacent to the first data line and on either side of the first data line, the adjacent data lines coupled to unselected strings of memory cells; applying an enable voltage to select gate drain transistors to operably couple the first string of memory cells to the first data line; and applying a disable voltage to select gate drain transistors that couple the unselected strings of memory cells to the adjacent data lines.

16 . The method of claim 15 , further comprising applying a disable voltage to control gates of select gate source transistors.

17 . The method of claim 16 , further comprising applying a positive voltage to a source line coupled to the select gate source transistors.

18 . The method of claim 15 , wherein applying the page buffer data to the first data line comprises enabling programming transistors coupled between the page buffer and the first data line.

19 . The method of claim 15 , wherein the first data line is one of a plurality of even data lines alternating with a plurality of odd data lines of the plurality of vertically stacked alternating data lines.

20 . The method of claim 19 , wherein the even data lines are selected during programming of the selected memory cell and the odd data lines are unselected during the programming of the selected memory cell.

Assignees

• Micron Technology Inc

Inventors

• Sakui Koji

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3427 Primary

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title