Partial page memory operations

Patent metadata

Field	Value
Publication number	US-2016232979-A1
Application number	US-201615131719-A
Country	US
Kind code	A1
Filing date	Apr 18, 2016
Priority date	Oct 26, 2012
Publication date	Aug 11, 2016
Grant date	—

Abstract

Apparatuses may include a memory block with strings of memory cells formed in a plurality of tiers. The apparatus may further comprise access lines and data lines shared by the strings, with the access lines coupled to the memory cells corresponding to a respective tier of the plurality of tiers. The memory cells corresponding to at least a portion of the respective tier may comprise a respective page of a plurality of pages. Subsets of the data lines may be mapped into a respective partial page of a plurality of partial pages of the respective page. Each partial page may be independently selectable from other partial pages. Additional apparatuses and methods are disclosed.

First claim

What is claimed is:

1 . An apparatus comprising a memory block, the memory block comprising:
strings of memory cells formed in a plurality of tiers; access lines shared by the strings, each access line coupled to the memory cells corresponding to a respective tier of the plurality of tiers, the memory cells corresponding to at least a portion of the respective tier comprising a respective page of a plurality of pages; and data lines shared by the strings, the data lines comprising a plurality of subsets of data lines, each subset of data lines being mapped into a respective partial page of a plurality of partial pages of the respective page, each partial page independently selectable from other partial pages within the respective page.

2 . The apparatus of claim 1 , wherein each of the plurality of partial pages comprises a tile.

3 . The apparatus of claim 1 , wherein each of the plurality of partial pages comprises a tile group, each tile group including a plurality of tiles.

4 . The apparatus of claim 1 , wherein each of the plurality of partial pages comprises a tile group gather, each tile group gather including a plurality of tile groups.

5 . The apparatus of claim 4 , wherein the plurality of tile groups included in the tile group gather are proximately related according to a numerical address sequence.

6 . The apparatus of claim 4 , wherein at least one of the plurality of tile groups included in the tile group gather is proximately unrelated according to a numerical address sequence.

7 . The apparatus of claim 1 , further comprising:
a control unit to map write data into the respective page of the respective tier such that a first portion of the write data will be programmed into a first partial page of the partial pages, and a second portion of the write data will be programmed into a second partial page of the partial pages, upon receiving a command to write the write data at the control unit.

8 . The apparatus of claim 7 , wherein the control unit is configured to:
trigger programming the write data in the respective page of the respective tier prior to a page buffer associated with the block being filled.

9 . The apparatus of claim 7 , wherein the control unit is configured to:
program the first portion into the first partial page; and program the second portion into the second partial page after programming the first portion into the first partial page and without first erasing the memory block.

10 . An apparatus comprising a memory block, the memory block comprising:
strings of memory cells formed in a plurality of tiers; access lines shared by the strings, each access line coupled to the memory cells corresponding to a respective tier of the plurality of tiers, the memory cells corresponding to at least a portion of the respective tier comprising a respective page of a plurality of pages; and data lines shared by the strings, the data lines comprising a plurality of subsets of data lines, each subset of data lines being mapped into a respective partial page of a plurality of partial pages of the respective page including a first partial page and a second partial page, each partial page independently selectable from other partial pages such that a single memory operation can be independently performed on the first partial page and the second partial page within the respective page.

11 . The apparatus of claim 1 , further comprising:
a control unit to select at least one of the first partial page or the second partial page based on column addresses associated with data for the single memory operation.

12 . A method comprising:
receiving data from a host; mapping the data into a page selected from a plurality of pages, each of the plurality of pages corresponding to one of a plurality of tiers in a memory block, the page comprising a plurality of partial pages including a first partial page and a second partial page, each partial page independently selectable from other partial pages, the mapping including mapping a first portion of the data into the first partial page, and a second portion of the data into the second partial page; programming the first portion of the data into the first partial page; and programming the second portion of the data into the second partial page independently of the first portion of the data programmed in the first partial page.

13 . The method of claim 12 , wherein the receiving comprises:
initiating a page program including programming of the first partial page before a page buffer receiving the data is filled.

14 . The method of claim 12 , wherein the mapping of the data comprises:
splitting the data into the portions based at least in part on a size of the page and a number of the partial pages.

15 . The method of claim 12 , wherein the mapping of the data comprises:
selecting, as the first and second partial pages, two of the plurality of partial pages proximately related according to a numerical address sequence.

16 . The method of claim 12 , wherein the mapping of the data comprises:
selecting, as the first and second partial pages, two of the plurality of partial pages proximately unrelated according to a numerical address sequence.

17 . The method of claim 12 , wherein the programming of the first portion comprises:
activating a first set of data lines corresponding to the first partial page; and disabling other data lines including a second set of data lines corresponding to the second partial page.

18 . The method of claim 17 , wherein the programming of the second portion comprises:
activating the second set of data lines; and disabling other data lines including the first set of data lines.

19 . The method of claim 12 , wherein the programming of the second portion of the data comprises programming the second portion of the data without first erasing the selected page after programming the first portion of the data.

20 . The method of claim 12 , wherein the programming of the second portion comprises:
refraining from programming the first partial page.

Assignees

• Micron Technology Inc

Inventors

• Abraham Michael
• Tanaka Tomoharu
• Kawai Koichi
• Einaga Yuichi

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/107 Primary

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title