Memory device comprising first through fourth transistors

Patent metadata

Field	Value
Publication number	US-11205461-B2
Application number	US-201816625826-A
Country	US
Kind code	B2
Filing date	Jun 19, 2018
Priority date	Jun 27, 2017
Publication date	Dec 21, 2021
Grant date	Dec 21, 2021

Abstract

A memory device that operates at high speed is provided.The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

First claim

The invention claimed is:

1. A memory device comprising:
a first memory cell;
a second memory cell;
a first wiring;
a second wiring;
a first switch;
a second switch;
a third transistor;
a fourth transistor; and
a sense amplifier,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor,
wherein the second memory cell comprises a second transistor and a second capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second capacitor,
wherein the sense amplifier comprises a first node and a second node,
wherein the first wiring is electrically connected to the first node through the first switch,
wherein the second wiring is electrically connected to the second node through the second switch,
wherein the sense amplifier amplifies a potential difference between the first node and the second node,
wherein one of a source and a drain of the third transistor is electrically connected to the first node,
wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, and
wherein a gate of the third transistor is electrically connected to the first wiring.

2. The memory device according to claim 1 , wherein the first switch and the second switch comprise a transistor.

3. The memory device according to claim 1 , wherein the first switch and the second switch are composed of an n-channel transistor, and
wherein the sense amplifier is composed of a single-polarity circuit using an n-channel transistor.

4. The memory device according to claim 1 , wherein the first transistor and the second transistor comprise an oxide semiconductor in a channel formation region.

5. The memory device according to claim 1 , wherein the first memory cell and the second memory cell are provided over the sense amplifier.

6. The memory device according to claim 1 , further comprising a fifth transistor and a sixth transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the second node,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, and
wherein a gate of the fifth transistor is electrically connected to the second wiring.

7. The memory device according to claim 6 , wherein the memory device has a function of setting a potential of the first wiring to a potential corresponding to data retained in the first memory cell and then turning on the fourth transistor and the sixth transistor.

8. The memory device according to claim 7 , wherein the memory device has a function of precharging the first wiring and the second wiring and then setting the potential of the first wiring to the potential corresponding to the data retained in the first memory cell.

9. A memory device comprising:
first to fourth memory cells;
first to fourth wirings;
first to fourth switches;
a fifth transistor;
a sixth transistor; and
a sense amplifier,
wherein the first memory cell comprises a first transistor and a first capacitor,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to the first capacitor,
wherein the second memory cell comprises a second transistor and a second capacitor,
wherein one of a source and a drain of the second transistor is electrically connected to the second wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second capacitor,
wherein the third memory cell comprises a third transistor and a third capacitor,
wherein one of a source and a drain of the third transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to the third capacitor,
wherein the fourth memory cell comprises a fourth transistor and a fourth capacitor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the fourth capacitor,
wherein the sense amplifier comprises a first node and a second node,
wherein the first wiring is electrically connected to the first node through the first switch,
wherein the second wiring is electrically connected to the second node through the second switch,
wherein the third wiring is electrically connected to the first node through the third switch,
wherein the fourth wiring is electrically connected to the second node through the fourth switch,
wherein the sense amplifier amplifies a potential difference between the first node and the second node,
wherein one of a source and a drain of the fifth transistor is electrically connected to the first node,
wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, and
wherein a gate of the fifth transistor is electrically connected to the first wiring.

10. The memory device according to claim 9 , wherein the first to fourth switches comprise a transistor.

11. The memory device according to claim 9 , wherein the first to fourth switches are composed of an n-channel transistor, and
wherein the sense amplifier is composed of a single-polarity circuit using an n-channel transistor.

12. The memory device according to claim 9 , wherein the first to fourth transistors comprise an oxide semiconductor in a channel formation region.

13. The memory device according to claim 9 , wherein the first to fourth memory cells are provided over the sense amplifier.

14. The memory device according to claim 9 , a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor,
wherein one of a source and a drain of the seventh transistor is electrically connected to the second node,
wherein the other of the source and the drain of the seventh transistor is electrically connected to one of a source and a drain of the eighth transistor,
wherein a gate of the seventh transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the ninth transistor is electrically connected to the first node,
wherein the other of the source and the drain of the ninth transistor is electrically connected to one of a source and a drain of the tenth transistor,
wherein a gate of the ninth transistor is electrically connected to the third wiring,
wherein one of a source and a drain of the eleventh transistor is electrically connected to the second node,
wherein the other of the source and the drain of the eleventh transistor is electrically connected to one of a source and a drain of the twelfth transistor, and
wherein a gate of the eleventh transistor is electrically connected to the fourth wiring.

15. The memory device according to claim 14 , wherein the memory device has a function of setting a potential of the first wiring to a potential corresponding to data retained

Assignees

• Semiconductor Energy Lab

Inventors

• Onuki tatsuya
• Nagatsuka Shuhei

Classifications

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D84/0126

  the components including insulated gates, e.g. IGFETs · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C5/02

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title