Semiconductor device comprising memory devices each comprising sense amplifier and memory cell

Patent metadata

Field	Value
Publication number	US-10304523-B2
Application number	US-201514705698-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	May 9, 2014
Publication date	May 28, 2019
Grant date	May 28, 2019

Abstract

A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a plurality of memory devices, each of the plurality of memory devices comprises:
a sense amplifier;
four first transistors;
a first insulating film over the sense amplifier;
four bit lines over the first insulating film;
a second insulating film over the four bit lines; and
a memory cell including a second transistor and a capacitor over the second insulating film,

wherein, in each of the plurality of memory devices:
the four bit lines are arranged in a first layer in two rows and two columns; and
the four bit lines are electrically connected to the sense amplifier through the respective four first transistors.

2. The semiconductor device according to claim 1 ,
wherein, in each of the plurality of memory devices:
the two columns are adjacent to each other in a first direction and the two rows are adjacent to each other in a second direction perpendicular to the first direction; and
the four bit lines extend in the second direction.

3. The semiconductor device according to claim 2 ,
wherein the plurality of memory devices are arranged in the first direction at a pitch of a width of two bit lines or more.

4. The semiconductor device according to claim 2 ,
wherein each of plurality of memory devices further comprises a plurality of sense amplifiers including the sense amplifier, and
wherein the plurality of sense amplifiers are arranged in the second direction at a pitch of a length of one bit line or more.

5. The semiconductor device according to claim 1 ,
wherein each of the plurality of memory devices further includes:
two data lines over the memory cell; and
two third transistors,

wherein the two data lines are electrically connected to the sense amplifier through the respective two third transistors.

6. The semiconductor device according to claim 1 , wherein the second transistor is an oxide semiconductor transistor.

7. The semiconductor device according to claim 1 , wherein the four first transistors are silicon transistors.

8. The semiconductor device according to claim 1 ,
wherein each of the plurality of memory devices further comprises a plurality of memory cells including the memory cell, and
wherein a total number of the plurality of memory cells connected to each of the four bit lines is 3 to 32 in each of the plurality of memory devices.

9. The semiconductor device according to claim 1 , wherein capacitance of the capacitor is 0.1 fF to 10 fF.

10. An electronic device comprising:
the semiconductor device according to claim 1 ; and
a printed wiring board.

11. The semiconductor device according to claim 1 , further comprising a substrate on which are formed the sense amplifier and the memory cell,
wherein one of the four bit lines extends in a direction generally parallel to a top surface of the substrate, and
wherein the sense amplifier and the one of the four bit lines overlap, and
wherein the one of the four bit lines and the memory cell overlap.

12. The semiconductor device according to claim 1 , wherein a second layer comprising the sense amplifier and the first layer comprising the four bit lines are stacked in a vertical direction.

13. A semiconductor device comprising:
a plurality of sense amplifiers;
a plurality of first transistors;
a first insulating film over the plurality of sense amplifiers;
a plurality of bit lines over the first insulating film;
a second insulating film over the plurality of bit lines; and
a plurality of memory cells each including a second transistor and a capacitor over the second insulating film,
wherein the plurality of sense amplifiers are each electrically connected to four of the plurality of bit lines through respective four of the plurality of first transistors, and
wherein the four of the plurality of bit lines are arranged in a first layer in two rows and two columns.

14. The semiconductor device according to claim 13 ,
wherein a direction in which the plurality of bit lines extend is referred to as a second direction and a direction perpendicular to the second direction is referred to as a first direction,
wherein the plurality of bit lines are arranged two-dimensionally at a pitch of a first distance in the first direction and at a pitch of a second distance in the second direction, and
wherein the plurality of sense amplifiers are arranged two-dimensionally at a pitch of twice the first distance in the first direction and at a pitch of twice the second distance in the second direction.

15. The semiconductor device according to claim 13 ,
wherein a direction in which the plurality of bit lines extend is referred to as a second direction and a direction perpendicular to the second direction is referred to as a first direction,
wherein the plurality of bit lines are arranged two-dimensionally at a pitch of a third distance in the first direction and at a pitch of a fourth distance in the second direction, and
wherein the plurality of sense amplifiers are arranged two-dimensionally at a pitch of four times the third distance in the first direction and at a pitch of the fourth distance in the second direction.

16. The semiconductor device according to claim 15 ,
wherein sense amplifiers adjacent to each other in the second direction of the plurality of sense amplifiers are shifted from each other by a fifth distance in the first direction, and
wherein the fifth distance is shorter than the third distance.

17. The semiconductor device according to claim 13 , further comprising:
a plurality of data lines over the plurality of memory cells; and
a plurality of third transistors,
wherein the plurality of sense amplifiers are each electrically connected to two of the plurality of data lines through respective two of the plurality of third transistors, and
wherein the plurality of data lines are each electrically connected to sense amplifiers adjacent to each other of the plurality of sense amplifiers through respective two of the plurality of third transistors.

18. The semiconductor device according to claim 13 , wherein the second transistor is an oxide semiconductor transistor.

19. The semiconductor device according to claim 13 , wherein the plurality of first transistors are silicon transistors.

20. The semiconductor device according to claim 13 , wherein a number of memory cells connected to each of the plurality of bit lines is 3 to 32.

21. The semiconductor device according to claim 13 , wherein capacitance of the capacitor is 0.1 fF to 10 fF.

22. An electronic device comprising:
the semiconductor device according to claim 13 ; and
a printed wiring board.

23. The semiconductor device according to claim 13 , further comprising a substrate on which are formed the plurality of sense amplifiers and the plurality of memory cells,
wherein one of the plurality of bit lines extends in a direction generally parallel to a top surface of the substrate, and
wherein one of the plurality of sense amplifiers and the one of the four bit lines overlap, and
wherein the one of the plurality of bit lines and one of the plurality of memory cells overlap.

24. A memory device comprising:
a sense amplifier;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a first insulating film over the sense amplifier;
a first bit line over the first insulating film;
a second bit line over the first insulating film;
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Assignees

• Semiconductor Energy Lab

Inventors

• Kato Kiyoshi
• Onuki tatsuya

Classifications

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title