Electronic device

Patent metadata

Field	Value
Publication number	US-9627034-B2
Application number	US-201615153175-A
Country	US
Kind code	B2
Filing date	May 12, 2016
Priority date	May 15, 2015
Publication date	Apr 18, 2017
Grant date	Apr 18, 2017

Abstract

Provided is an electronic device including a circuit for reading data from a memory cell that can store multilevel data. The electronic device includes a memory cell array region, N sense amplifier regions, and switching elements. The memory cell array region includes memory cells that store, when (N+1)-level data is stored, the (N+1)-level data as different potentials. Each of the N sense amplifier regions compares a read potential, which depends on a charge released to a bit line and a wiring or the like connected thereto, with a reference potential and performs amplification. Each of the switching elements electrically isolates a sense amplifier region from the other sense amplifier regions after all of the N sense amplifier regions are electrically connected to the bit line. Each of the sense amplifier regions can output a write potential to the bit line.

First claim

What is claimed is:

1. An electronic device comprising:
a bit line;
first to N-th switching elements; and
first to N-th sense amplifier regions,
wherein the first to the N-th sense amplifier regions each include a first terminal,
wherein the first to the (N−1)-th sense amplifier regions each include a second terminal,
wherein a first terminal of an n-th sense amplifier region, a second terminal of an n-th sense amplifier region, a first terminal of an (n+1)-th sense amplifier region, and a second terminal of an (n+1)-th sense amplifier region are arranged in this order in a circuit diagram,
wherein the first switching element is between the bit line and the first terminal of the first sense amplifier region,
wherein the first switching element is configured to electrically connect or electrically isolate the bit line and the first terminal of the first sense amplifier region,
wherein an (n+1)-th switching element is between the second terminal of the n-th sense amplifier region and the first terminal of the (n+1)-th sense amplifier region,
wherein the (n+1)-th switching element is configured to electrically connect or electrically isolate the second terminal of the n-th sense amplifier region and the first terminal of the (n+1)-th sense amplifier region,
wherein the first to the N-th sense amplifier regions each comprise a sense amplifier and a switch that operates in accordance with an output of the sense amplifier,
wherein the switch is configured to electrically connect or electrically isolate the first terminal and the second terminal,
wherein at the time when the sense amplifiers terminate an amplification process, (A) the bit line is electrically connected to the first terminal of an m-th sense amplifier region and the first terminal and the second terminal are electrically isolated from each other in each of the m-th to the (N−1)-th sense amplifier regions, or (B) the bit line is electrically connected to the first terminal of the N-th sense amplifier region,
wherein a potential of the bit line corresponds to a read potential, and
wherein N is an integer greater than or equal to 2, n is an integer greater than or equal to 1 and less than or equal to (N−1), and m is an integer that is determined in accordance with the read potential and is greater than or equal to 1 and less than or equal to (N+1).

2. The electronic device according to claim 1 , wherein each of the first to the (N−1)-th sense amplifier regions is configured to supply a write potential to the first terminal in accordance with one of or both a first output signal and a second output signal of the sense amplifier.

3. The electronic device according to claim 2 , wherein each of the first to the (N−1)-th sense amplifier regions is configured to electrically connect or electrically isolate the first terminal and the second terminal in accordance with one of or both a first output signal and a second output signal of the sense amplifier.

4. The electronic device according to claim 2 , wherein each of the first to the (N−1)-th sense amplifier regions is configured such that the first terminal and the second terminal are electrically isolated from each other when the write potential is supplied to the first terminal.

5. The electronic device according to claim 2 , wherein a write potential of the n-th sense amplifier region is configured to be higher than a write potential of the (n+1)-th sense amplifier region.

6. The electronic device according to claim 2 ,
wherein a potential of the first terminal is configured to be input to a first input terminal of the sense amplifier in a first period,
wherein a reference potential is configured to be input to a second input terminal of the sense amplifier in a second period, and
wherein the first period and the second period overlap with each other.

7. The electronic device according to claim 2 , wherein a reference potential of the n-th sense amplifier region is configured to be higher than a write potential of the (n+1)-th sense amplifier region.

8. The electronic device according to claim 2 , wherein a write potential of each of the first to the (N−1)-th sense amplifier regions is configured to be equal to the first output signal of the sense amplifier.

9. An electronic device comprising:
a bit line;
a transistor;
a capacitor;
first to N-th switching elements; and
first to N-th sense amplifier regions,
wherein a first terminal of the transistor is electrically connected to the bit line,
wherein a second terminal of the transistor is electrically connected to the capacitor,
wherein the transistor comprises an oxide semiconductor material,
wherein the first to the N-th sense amplifier regions each comprise a first terminal, a sense amplifier, and a switching element,
wherein the first to an (N−1)-th sense amplifier regions each comprise a second terminal,
wherein a first terminal of the first switching element is electrically connected to the bit line,
wherein a second terminal of the first switching element is electrically connected to the first terminal of the first sense amplifier region,
wherein a first terminal of an (n+1)-th switching element is electrically connected to a second terminal of an n-th sense amplifier region,
wherein a second terminal of the (n+1)-th switching element is electrically connected to a first terminal of an (n+1)-th sense amplifier region,
wherein a first terminal of a switching element of an n-th sense amplifier region is electrically connected to a first terminal of the n-th sense amplifier region,
wherein a second terminal of the switching element of the n-th sense amplifier region is electrically connected to the second terminal of the n-th sense amplifier region,
wherein a sense amplifier of the n-th sense amplifier region is electrically connected to the first terminal of the n-th sense amplifier region,
wherein the sense amplifier of the n-th sense amplifier region is electrically connected to the first terminal of the switching element of the n-th sense amplifier region, and
wherein N is an integer greater than or equal to 2, and n is an integer greater than or equal to 1 and less than or equal to (N−1).

10. The electronic device according to claim 9 , wherein a write potential of the n-th sense amplifier region is configured to be higher than a write potential of the (n+1)-th sense amplifier region.

11. The electronic device according to claim 9 , wherein a reference potential of the n-th sense amplifier region is configured to be higher than a write potential of the (n+1)-th sense amplifier region.

12. The electronic device according to claim 9 , wherein the first to N-th switching elements comprise an oxide semiconductor.

13. The electronic device according to claim 9 , wherein the oxide semiconductor comprises In, Ga, or Zn.

14. An electronic device comprising:
a bit line;
a transistor;
a capacitor;
first to N-th switching elements; and
first to N-th sense amplifier regions,
wherein a first terminal of the transistor is electrically connected to the bit line,
wherein a second terminal of the transistor is electrically connected to the capacitor,
wherein the transistor comprises an oxide semiconductor material,
wherein the first to the N-th sense amplifier regions each comprise a first terminal, a sense amplifier, and a switching element,
wherein the first to an (N−1)-th sense amplifier regions each comprise a second terminal,
wherein a first terminal of the first switching element is electrically connected to the bit line,
wherein a second terminal of the first switching element is electrically connected to the first term

Assignees

• Semiconductor Energy Lab

Inventors

• Matsuzaki Takanori

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• H01L29/24

  Electricity · mapped topic

• H01L27/1255

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic