Semiconductor device, driver IC, computer and electronic device

Patent metadata

Field	Value
Publication number	US-10032492-B2
Application number	US-201715455226-A
Country	US
Kind code	B2
Filing date	Mar 10, 2017
Priority date	Mar 18, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A semiconductor device that is novel, is capable of high-speed operation, consumes low power, or occupies a small area is provided. The semiconductor device includes a memory portion, a control circuit, and a plurality of wirings. The memory portion includes a plurality of memory circuits. The memory circuit includes a memory cell. The memory cell is electrically connected to a wiring. A first signal that indicates the amount of data that are written to or read from the memory portion is supplied to the control circuit. The control circuit has the function of controlling the number of the wirings to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory portion; and
a control circuit,
wherein the memory portion comprises a plurality of memory circuits,
wherein each of the plurality of memory circuits comprises a memory cell and a wiring,
wherein the memory cell is electrically connected to the wiring,
wherein the control circuit is supplied with a first signal that indicates the amount of data to be written to the memory portion or the amount of data to be read from the memory portion, and
wherein the control circuit is configured to control the number of the plurality of memory circuits to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal.

2. The semiconductor device according to claim 1 ,
wherein the control circuit is supplied with an address signal, and
wherein the second signal is generated on the basis of the first signal and the address signal.

3. A driver IC comprising:
a frame memory comprising the semiconductor device according to claim 1 ;
a controller; and
a source driver.

4. A computer comprising:
the semiconductor device according to claim 1 ;
an input device;
an output device; and
a CPU.

5. An electronic device comprising:
the semiconductor device according to claim 1 ; and
at least one of a display portion, a microphone, a speaker, and a control key.

6. A semiconductor device comprising:
a memory portion; and
a control circuit,
wherein the memory portion comprises a plurality of memory circuits,
wherein each of the plurality of memory circuits comprises a memory cell, a first wiring, a second wiring and an amplifier circuit,
wherein the memory cell is electrically connected to the first wiring and the second wiring,
wherein the amplifier circuit is electrically connected to the second wiring,
wherein the control circuit is supplied with a first signal that indicates the amount of data to be written to the memory portion or the amount of data to be read from the memory portion,
wherein the control circuit is configured to control the number of the plurality of memory circuits to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal, and
wherein the control circuit is configured to control the number of the plurality of memory circuits to which a third signal for operating the amplifier circuit is simultaneously supplied on the basis of the first signal.

7. The semiconductor device according to claim 6 ,
wherein the amplifier circuit is configured to temporarily retain data that have been read from the memory cell.

8. The semiconductor device according to claim 6 ,
wherein the memory cell comprises a transistor,
wherein the transistor comprises an oxide semiconductor in a channel formation region, and
wherein the memory cell is stacked over the amplifier circuit.

9. The semiconductor device according to claim 6 ,
wherein the control circuit is supplied with an address signal, and
wherein the second signal is generated on the basis of the first signal and the address signal.

10. A driver IC comprising:
a frame memory comprising the semiconductor device according to claim 6 ;
a controller; and
a source driver.

11. A computer comprising:
the semiconductor device according to claim 6 ;
an input device;
an output device; and
a CPU.

12. An electronic device comprising:
the semiconductor device according to claim 6 ; and
at least one of a display portion, a microphone, a speaker, and a control key.

13. A semiconductor device comprising:
a memory portion; and
a control circuit,
wherein the memory portion comprises a plurality of memory circuits,
wherein each of the plurality of memory circuits comprises a memory cell, a first wiring, a second wiring and an amplifier circuit,
wherein the memory cell is electrically connected to the first wiring and the second wiring,
wherein the amplifier circuit is electrically connected to the second wiring,
wherein the control circuit is supplied with a first signal that indicates the number of the plurality of memory circuits to be selected,
wherein the control circuit is configured to control the number of the plurality of memory circuits to which a second signal for selecting the memory cell is simultaneously supplied on the basis of the first signal, and
wherein the control circuit is configured to control the number of the plurality of memory circuits to which a third signal for operating the amplifier circuit is simultaneously supplied on the basis of the first signal.

14. The semiconductor device according to claim 13 ,
wherein the amplifier circuit is configured to temporarily retain data that have been read from the memory cell.

15. The semiconductor device according to claim 13 ,
wherein the memory cell comprises a transistor,
wherein the transistor comprises an oxide semiconductor in a channel formation region, and
wherein the memory cell is stacked over the amplifier circuit.

16. The semiconductor device according to claim 13 ,
wherein the control circuit is supplied with an address signal, and
wherein the second signal is generated on the basis of the first signal and the address signal.

17. A driver IC comprising:
a frame memory comprising the semiconductor device according to claim 13 ;
a controller; and
a source driver.

18. A computer comprising:
the semiconductor device according to claim 13 ;
an input device;
an output device; and
a CPU.

19. An electronic device comprising:
the semiconductor device according to claim 13 ; and
at least one of a display portion, a microphone, a speaker, and a control key.

Assignees

• Semiconductor Energy Lab

Inventors

• Onuki tatsuya

Classifications

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C8/10

  Decoders · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C7/065 Primary

  Differential amplifiers of latching type · CPC title