Semiconductor device with stacked structure of memory cells over sensing amplifiers, circuit board, and electronic device

Patent metadata

Field	Value
Publication number	US-9704562-B2
Application number	US-201514872535-A
Country	US
Kind code	B2
Filing date	Oct 1, 2015
Priority date	Oct 10, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array including a first memory cell and a second memory cell; and a sense amplifier circuit including a first sense amplifier and a second sense amplifier. The cell array is over the sense amplifier circuit. The first sense amplifier is electrically connected to the first memory cell through a first wiring BL. The second sense amplifier is electrically connected to the second memory cell through a second wiring BL. The first sense amplifier and the second sense amplifier are electrically connected to a wiring GBL. The sense amplifier circuit is configured to select one of a potential of the first wiring BL and a potential of the second wiring BL and output the selected potential to the wiring GBL.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a sense amplifier circuit comprising a first sense amplifier and a second sense amplifier; and
a cell array over the sense amplifier circuit, the cell array comprising first to fourth memory cells,
wherein the first memory cell and the second memory cell are electrically connected to the first sense amplifier through a first bit line and a second bit line, respectively,
wherein the third memory cell and the fourth memory cell are electrically connected to the second sense amplifier through a third bit line and a fourth bit line, respectively,
wherein each of the first sense amplifier and the second sense amplifier is electrically connected to a first global bit line and a second global bit line, and
wherein the sense amplifier circuit is configured to select one of potentials of the first to fourth bit lines and output a selected potential to the first global bit line or the second global bit line.

2. The semiconductor device according to claim 1 ,
wherein the first sense amplifier comprises a first switch circuit,
wherein the second sense amplifier comprises a second switch circuit,
wherein each of the first switch circuit and the second switch circuit is electrically connected to the first global bit line and the second global bit line,
and
wherein the cell array is provided over the first switch circuit, the second switch circuit, the first global bit line, and the second global bit line.

3. The semiconductor device according to claim 1 ,
wherein each of the first memory cell and the second memory cell comprises a transistor and a capacitor,
wherein one of a source and a drain of the transistor is electrically connected to the capacitor, and
wherein the transistor includes an oxide semiconductor in a channel formation region.

4. The semiconductor device according to claim 3 ,
wherein the capacitor is provided over the transistor, and
wherein the capacitor includes a region overlapping with the oxide semiconductor.

5. A circuit board comprising:
an electronic component comprising the semiconductor device according to claim 1 ; and
a printed circuit board.

6. An electronic device comprising:
the circuit board according to claim 5 ; and
at least one of a display portion, a microphone, a speaker, and an operation key.

7. An electronic device comprising:
the semiconductor device according to claim 1 ; and
at least one of a display portion, a microphone, a speaker, and an operation key.

8. The semiconductor device according to claim 1 ,
wherein each of the first sense amplifier and the second sense amplifier includes a plurality of transistors, and
wherein each of the plurality of transistors comprises silicon.

9. A semiconductor device comprising a memory circuit, the memory circuit comprising:
a sense amplifier circuit comprising a first sense amplifier and a second sense amplifier; and
a cell array over the sense amplifier circuit, the cell array comprising first to fourth memory cells,
wherein the first memory cell and the second memory cell are electrically connected to the first sense amplifier through a first bit line and a second bit line, respectively,
wherein the third memory cell and the fourth memory cell are electrically connected to the second sense amplifier through a third bit line and a fourth bit line, respectively, and
wherein each of the first sense amplifier and the second sense amplifier are electrically connected to a first global bit line and a second global bit line.

10. The semiconductor device according to claim 9 ,
wherein the first sense amplifier comprises a first switch circuit,
wherein the second sense amplifier comprises a second switch circuit, and
wherein each of the first switch circuit and the second switch circuit is electrically connected to the first global bit line and the second global bit line.

11. The semiconductor device according to claim 10 , wherein the cell array is provided over the first switch circuit, the second switch circuit, the first global bit line, and the second global bit line.

12. The semiconductor device according to claim 9 ,
wherein each of the first memory cell and the second memory cell comprises a transistor and a capacitor,
wherein one of a source and a drain of the transistor is electrically connected to the capacitor, and
wherein the transistor includes an oxide semiconductor in a channel formation region.

13. The semiconductor device according to claim 12 ,
wherein the capacitor is provided over the transistor, and
wherein the capacitor includes a region overlapping with the oxide semiconductor.

14. A circuit board comprising:
an electronic component comprising the semiconductor device according to claim 9 ; and
a printed circuit board.

15. An electronic device comprising:
the semiconductor device according to claim 9 ; and
at least one of a display portion, a microphone, a speaker, and an operation key.

16. The semiconductor device according to claim 9 ,
wherein each of the first sense amplifier and the second sense amplifier includes a plurality of transistors, and
wherein each of the plurality of transistors comprises silicon.

17. A semiconductor device comprising a memory circuit, the memory circuit comprising:
a sense amplifier circuit comprising a plurality of sense amplifiers; and
a cell array over the sense amplifier circuit, the cell array comprising a plurality of memory cells,
wherein the plurality of memory cells are electrically connected to the plurality of sense amplifiers through a plurality of bit lines,
wherein the sense amplifier circuit is electrically connected to a main amplifier through a plurality of global bit lines,
wherein the number of the plurality of bit lines is larger than the number of the plurality of global bit lines, and
wherein the cell array is provided over the sense amplifier circuit, the main amplifier, and the plurality of global bit lines.

18. The semiconductor device according to claim 17 ,
wherein each of the plurality of sense amplifiers comprises a switch circuit electrically connected to two of the plurality of global bit lines.

19. The semiconductor device according to claim 17 ,
wherein the sense amplifier circuit includes a plurality of transistors, and
wherein each of the plurality of transistor comprises silicon.

20. The semiconductor device according to claim 17 ,
wherein each of the plurality of memory cells comprises a transistor and a capacitor,
wherein one of a source and a drain of the transistor is electrically connected to the capacitor, and
wherein the transistor includes an oxide semiconductor in a channel formation region.

21. The semiconductor device according to claim 20 ,
wherein the capacitor is provided over the transistor, and
wherein the capacitor includes a region overlapping with the oxide semiconductor.

22. An electronic device comprising:
the semiconductor device according to claim 17 ; and
at least one of a display portion, a microphone, a speaker, and an operation key.

Assignees

• Semiconductor Energy Lab

Inventors

• Onuki tatsuya
• Kato Kiyoshi
• Uesugi Wataru
• Ishizu Takahiko

Classifications

• G11C11/4094

  Bit-line management or control circuits · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091 Primary

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• G11C2213/71

  Three dimensional array · CPC title