Semiconductor device and electronic device

Patent metadata

Field	Value
Publication number	US-9542977-B2
Application number	US-201514681570-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 11, 2014
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.

First claim

What is claimed is:

1. A semiconductor device comprising:
a memory circuit comprising a first transistor over a single crystal semiconductor substrate, the first transistor including a first channel formation region provided in the single crystal semiconductor substrate;
an insulating layer over the memory circuit; and
an amplifier circuit comprising a second transistor over the insulating layer, the second transistor including a second channel formation region provided in an oxide semiconductor layer,
wherein the memory circuit and the amplifier circuit are electrically connected to each other, and
wherein the memory circuit and the amplifier circuit comprise mutually overlapping regions.

2. The semiconductor device according to claim 1 , wherein the first channel formation region and the second channel formation region comprise mutually overlapping regions.

3. The semiconductor device according to claim 1 , wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor.

4. The semiconductor device according to claim 1 , further comprising a conductive layer that is provided in an opening formed in the insulating layer and electrically connects the memory circuit and the amplifier circuit.

5. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer contains In, Zn, and a metal selected from Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf.

6. An electronic device comprising the semiconductor device according to claim 1 and at least one of a display device, a speaker, and a microphone.

7. A semiconductor device comprising:
an integrated circuit comprising a first transistor over a single crystal semiconductor substrate, the first transistor including a first channel formation region provided in the single crystal semiconductor substrate;
an insulating layer over the integrated circuit;
a memory circuit comprising a second transistor over the insulating layer, the second transistor including a second channel formation region provided in a first oxide semiconductor layer;
an amplifier circuit comprising a third transistor over the insulating layer, the third transistor including a third channel formation region provided in a second oxide semiconductor layer,
wherein the memory circuit and the amplifier circuit are electrically connected to each other,
wherein the amplifier circuit and the integrated circuit are electrically connected to each other, and
wherein the integrated circuit and one of the memory circuit and the amplifier circuit comprise mutually overlapping regions.

8. The semiconductor device according to claim 7 , wherein the first channel formation region and one of the second and third channel formation regions comprise mutually overlapping regions.

9. The semiconductor device according to claim 7 , wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor.

10. The semiconductor device according to claim 7 , further comprising a conductive layer that is provided in an opening formed in the insulating layer and electrically connects the integrated circuit and the amplifier circuit.

11. The semiconductor device according to claim 7 , further comprising:
a second insulating layer between the second transistor and the third transistor; and
a conductive layer that is provided in an opening formed in the second insulating layer and electrically connects the memory circuit and the amplifier circuit,
wherein the memory circuit and the amplifier circuit comprise mutually overlapping regions.

12. The semiconductor device according to claim 11 , wherein the memory circuit is provided over the amplifier circuit.

13. The semiconductor device according to claim 7 , wherein the first and second oxide semiconductor layers each contain In, Zn, and a metal selected from Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf.

14. An electronic device comprising the semiconductor device according to claim 7 and at least one of a display device, a speaker, and a microphone.

15. A semiconductor device comprising:
an integrated circuit comprising a first transistor over a single crystal semiconductor substrate, the first transistor including a first channel formation region provided in the single crystal semiconductor substrate;
a first insulating layer over the integrated circuit;
a memory circuit comprising a second transistor over the first insulating layer, the second transistor including a second channel formation region provided in a first oxide semiconductor layer;
a second insulating layer over the memory circuit; and
an amplifier circuit comprising a third transistor over the second insulating layer, the third transistor including a third channel formation region provided in a second oxide semiconductor layer,
wherein the memory circuit and the amplifier circuit are electrically connected to each other,
wherein the amplifier circuit and the integrated circuit are electrically connected to each other, and
wherein the integrated circuit, the memory circuit, and the amplifier circuit comprise mutually overlapping regions.

16. The semiconductor device according to claim 15 , further comprising:
a first conductive layer that is provided in a first opening formed in the first and second insulating layers and electrically connects the integrated circuit and the amplifier circuit; and
a second conductive layer that is provided in a second opening formed in the second insulating layer and electrically connects the memory circuit and the amplifier circuit.

17. The semiconductor device according to claim 15 , wherein the second channel formation region and the third channel formation region comprise mutually overlapping regions.

18. The semiconductor device according to claim 15 , wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor.

19. The semiconductor device according to claim 15 , wherein the first and second oxide semiconductor layers each contain In, Zn, and a metal selected from Al, Ti, Ga, Y, Zr, La, Ce, Nd, and Hf.

20. An electronic device comprising the semiconductor device according to claim 15 and at least one of a display device, a speaker, and a microphone.

Assignees

• Semiconductor Energy Lab

Inventors

• Onuki tatsuya
• Kato Kiyoshi
• Shionoiri Yutaka
• Atsumi Tomoaki
• Matsuzaki Takanori
• Inoue Hiroki
• Nagatsuka Shuhei
• Yakubo Yuto

Classifications

• G11C5/025 Primary

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4091

  Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating · CPC title

• H01L29/24

  Electricity · mapped topic

• H01L27/1207

  Electricity · mapped topic