Two-stage top source drain epitaxy formation for vertical field effect transistors enabling gate last formation

Patent metadata

Field	Value
Publication number	US-11164787-B2
Application number	US-201916720060-A
Country	US
Kind code	B2
Filing date	Dec 19, 2019
Priority date	Dec 19, 2019
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

A semiconductor structure including a bottom source drain region arranged on a substrate, a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region, a metal gate disposed on and around the semiconductor channel region, and a top source drain region above the semiconductor channel region and comprising a first doped epitaxy region and a second doped epitaxy region.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed on and around the semiconductor channel region; and
a top source drain region above the semiconductor channel region and comprising a first doped epitaxy region and a second doped epitaxy region, wherein the first doped epitaxy region has a dopant concentration of at least about 5×10 21 atoms/cm 3 , and the second doped epitaxy region has a dopant concentration of at least about 4×10 20 atoms/cm 3 .

2. The semiconductor structure according to claim 1 , further comprising:
a bottom spacer separating the bottom source drain region from the metal gate.

3. The semiconductor structure according to claim 1 , wherein a width of the first doped epitaxy region of the top source drain region is substantially equal to a width of the semiconductor channel region, and wherein a width of the second doped epitaxy region of the top source drain region is larger than the width of the semiconductor channel region.

4. The semiconductor structure according to claim 1 , further comprising:
sidewall spacers disposed along vertical sidewalls of the second doped epitaxy region and separating the second epitaxy doped region from an interlevel dielectric layer.

5. The semiconductor structure according to claim 1 , further comprising:
a contact on the second doped epitaxy region.

6. A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed on and around the semiconductor channel region;
a top source drain region above the semiconductor channel region and comprising a first epitaxy region and a second epitaxy region; and
a dielectric spacer disposed on the metal gate beneath the second epitaxy region, the dielectric spacer contacts vertical sidewalls of the metal gate and vertical sidewalls of the first epitaxy region.

7. The semiconductor structure according to claim 6 , wherein the dielectric spacer separates the metal gate from the top source drain region.

8. The semiconductor structure according to claim 6 , wherein a first portion of the dielectric spacer comprises a first height, and a second portion of the dielectric spacer comprises a second height.

9. The semiconductor structure according to claim 6 , further comprising:
a bottom spacer separating the bottom source drain region from the metal gate.

10. The semiconductor structure according to claim 6 , wherein a width of the first epitaxy region of the top source drain region is substantially equal to a width of the semiconductor channel region, and wherein a width of the second epitaxy region of the top source drain region is larger than the width of the semiconductor channel region.

11. The semiconductor structure according to claim 6 , further comprising:
sidewall spacers disposed along vertical sidewalls of the second epitaxy region and separating the second epitaxy region from an interlevel dielectric layer.

12. The semiconductor structure according to claim 6 , further comprising:
a contact on the second epitaxy region.

13. The semiconductor structure according to claim 6 , wherein the first epitaxy region has a dopant concentration of at least about 5×10 21 atoms/cm 3 , and the second epitaxy region has a dopant concentration of at least about 4×10 20 atoms/cm 3 .

14. A semiconductor structure comprising:
a bottom source drain region arranged on a substrate;
a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region;
a metal gate disposed on and around the semiconductor channel region; and
a top source drain region above the semiconductor channel region and comprising a first doped epitaxy region and a second doped epitaxy region above the first doped epitaxy region, wherein the second doped epitaxy comprises a lower dopant concentration than the first doped epitaxy region.

15. The semiconductor structure according to claim 14 , further comprising:
a bottom spacer separating the bottom source drain region from the metal gate.

16. The semiconductor structure according to claim 14 , wherein a width of the first doped epitaxy region of the top source drain region is substantially equal to a width of the semiconductor channel region, and wherein a width of the second doped epitaxy region of the top source drain region is larger than the width of the semiconductor channel region.

17. The semiconductor structure according to claim 14 , further comprising:
sidewall spacers disposed along vertical sidewalls of the second doped epitaxy region and separating the second epitaxy doped region from an interlevel dielectric layer.

18. The semiconductor structure according to claim 14 , further comprising:
a contact on the second doped epitaxy region.

19. The semiconductor structure according to claim 14 , further comprising:
a dielectric spacer disposed on the metal gate beneath the second epitaxy region, the dielectric spacer contacts vertical sidewalls of the metal gate and vertical sidewalls of the first epitaxy region.

20. The semiconductor structure according to claim 1 , further comprising:
a dielectric spacer disposed on the metal gate beneath the second epitaxy region, the dielectric spacer contacts vertical sidewalls of the metal gate and vertical sidewalls of the first epitaxy region.

Assignees

• IBM

Inventors

• Reznicek Alexander
• Yeh Chun-Chen
• Liu Zuoguang
• Xie Ruilong

Classifications

• H10D84/0184

  Manufacturing their gate sidewall spacers · CPC title

• H10D84/016

  the components including vertical IGFETs · CPC title

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title