Vertical tunneling FinFET

Patent metadata

Field	Value
Publication number	US-10084080-B2
Application number	US-201514675298-A
Country	US
Kind code	B2
Filing date	Mar 31, 2015
Priority date	Mar 31, 2015
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

First claim

The invention claimed is:

1. A transistor, comprising:
a silicon substrate;
a doped drain region having a uniform doping type formed in the silicon substrate, the doped drain region having a planar surface;
a fin formed on the surface of the doped drain region and extending substantially perpendicular to the surface of the doped drain region, the fin including:
a channel region abutting the surface of the doped drain region; and
an epitaxial source region overlying and abutting the channel region;

an isolation layer on the surface of the doped drain region and abutting opposite sides of the channel region of the fin;
a multi-layer gate structure abutting opposite sides of the channel region of the fin, the multi-layer gate structure including a gate dielectric layer and a metal layer, the gate dielectric layer and the metal layer abutting the isolation layer;
a first gate contact on the multi-layer gate structure, the first gate contact being adjacent to a first side of the fin; and
a second gate contact on the multi-layer gate structure, the second gate contact being adjacent to a second side of the fin that is opposite to the first side.

2. The transistor of claim 1 wherein the gate dielectric layer of the multi-layer gate structure abuts the opposite sides of the channel region of the fin.

3. The transistor of claim 1 wherein the epitaxial source region includes two or more of boron, silicon germanium, phosphorous, arsenic, silicon, and silicon carbide.

4. The transistor of claim 1 wherein a dopant concentration of the epitaxial source region is at least 2-3 times greater than a dopant concentration of the doped drain region.

5. The transistor of claim 1 wherein a dopant concentration of the doped drain region is at least 10 times greater than a dopant concentration of the channel region.

6. The transistor of claim 1 wherein the fin has a fin width within a range of 6-12 nm.

7. The transistor of claim 1 wherein, during operation, a sub-threshold swing value is less than 30 mV/decade.

8. The transistor of claim 1 wherein, during operation, the transistor turns on in response to a voltage in the range of 0.1-1.0 V applied to the metal layer.

9. An integrated circuit including the transistor according to claim 1 .

10. The device of claim 1 wherein the isolation layer includes an oxide layer, the multi-layer gate structure being spaced apart from the doped drain region by the oxide layer.

11. A tunneling FET, comprising:
a drain region having a uniform doping type and a substantially planar top surface;
first and second fins, each of the first and second fins including:
source and channel regions arranged substantially perpendicular to the top surface of the drain region, the source and drain regions doped with ions of opposite polarity, and the channel region extending between the source and drain regions;

a first pair of dielectric layers abutting opposite sides of the channel region of the first fin;
a second pair of dielectric layers abutting opposite sides of the channel region of the second fin;
a metal gate structure having a first portion adjacent to a first side of the first fin, a second portion adjacent to a first side of the second fin, and a third portion between the first and second fins, the third portion of the metal gate structure being in contact with the first pair of dielectric layers and the second pair of dielectric layers, the metal gate structure being configured to control a vertical current flow in the channel regions of the first and second fins, between the respective source and drain regions, in response to an applied voltage;
a first gate contact on the first portion of the metal gate structure;
a second gate contact on the second portion of the metal gate structure; and
a third gate contact on the third portion of the metal gate structure.

12. The tunneling FET of claim 11 wherein the metal gate structure influences the vertical current flow from two sides of each of the first and second fins.

13. The device of claim 11 , further comprising:
an oxide layer on the drain region, each of the first pair of dielectric layers, the second pair of dielectric layers and the metal gate structure abutting an upper surface of the oxide layer.

14. A device, comprising:
a lightly doped silicon substrate;
a drain region formed in the silicon substrate, the drain region having a uniform doping type and a substantially planar top surface;
first and second fins extending substantially perpendicularly from the top surface of the drain region, each of the first and second fins including a respective channel overlying the drain region;
heavily doped source regions on top of the first and second fins;
isolation regions separating the first and second fins from neighboring fins;
a metal gate structure abutting opposite sides of the channel regions of each of the first and second fins, the metal gate structure including a metal gate;
an inter-layer dielectric; and
front side contacts to the heavily doped source regions on each of the first and second fins, the drain region, and the metal gate, the front side contacts to the source regions and the drain region being aligned along a first direction that is parallel to the planar top surface of the drain region, the front side contact to the metal gate being positioned between the first and second fins and spaced apart from the contacts to the source and drain regions along a second direction that is transverse to the first direction.

15. The device of claim 14 wherein the isolation regions include:
local isolation regions among a plurality of n-type fins,
local isolation regions among a plurality of p-type fins, and
trench isolation regions separating n-type and p-type devices from one another.

16. The device of claim 14 , wherein the metal gate structure includes a gate oxide positioned between the channel regions and the metal gate.

17. The device of claim 14 , further comprising silicon nitride sidewall spacers supporting the metal gate structure.

18. The device of claim 16 wherein the gate oxide includes one or more of silicon dioxide (SiO 2 ), hafnium oxide (HfO 2 ), and hafnium silicate compounds (HfSiON), (HfSiO).

19. The device of claim 14 wherein the metal gate includes one or more of titanium, titanium nitride, titanium carbide, tungsten, silicon boron carbon nitride, amorphous carbon, and aluminum oxide.

20. The device of claim 14 wherein the source regions are epitaxial source regions.

21. The device of claim 14 wherein the first and second fins and the drain region have similar polarity, and the source region have a polarity opposite that of the first and second fins and the drain region.

22. The device of claim 14 wherein the front side contacts to the heavily doped source regions, the drain region, and the metal gate have circular cross-sections.

23. The device of claim 14 , further comprising:
an insulating layer on the drain region, the insulating layer abutting side surfaces of the first and second fins, the metal gate structure being spaced apart from the drain region by the insulating layer.

Assignees

• St Microelectronics Inc

Inventors

• Liu Qing
• Zhang John H

Classifications

• H01L21/823487

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L27/092

  Electricity · mapped topic

• H01L21/823885

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic