Method and structure to control channel length in vertical FET device

Patent metadata

Field	Value
Publication number	US-9972494-B1
Application number	US-201615351747-A
Country	US
Kind code	B1
Filing date	Nov 15, 2016
Priority date	Nov 15, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A method of manufacturing a vertical field effect transistor includes an isotropic etch of a gate conductor to recess the gate and define the length of the transistor channel. A symmetric gate conductor geometry prior to the etch, in combination with the isotropic (i.e., lateral) etch, allows the effective vertical etch rate of the gate conductor to be independent of local pattern densities, resulting in a uniform channel length among plural transistors formed on a semiconductor substrate.

First claim

What is claimed is:

1. A method of making a vertical FET device comprising:
forming a plurality of fins over a semiconductor substrate, wherein the fins define an inter-fin spacing between sidewalls of adjacent fins;
forming a hard mask over top surfaces of the fins;
forming a gate dielectric directly over the sidewalls of the fins and over sidewalls of the hard masks;
forming a gate conductor directly over the gate dielectric, wherein the gate conductor thickness is substantially equal to the inter-fin spacing;
isotropically etching the gate conductor to form a functional gate; and
removing the hard mask to expose the top surfaces of the fins and removing the gate dielectric formed over the sidewalls of the hard mask prior to isotropically etching the gate conductor.

2. The method of claim 1 , further comprising forming bottom source/drain regions in the semiconductor substrate prior to forming the gate dielectric.

3. The method of claim 2 , wherein the bottom source/drain regions are formed by ion implantation into the semiconductor substrate.

4. The method of claim 2 , further comprising forming a bottom spacer over the bottom source/drain regions prior to forming the gate dielectric.

5. The method of claim 1 , wherein the gate conductor thickness over the sidewalls of the fins is substantially equal to the inter-fin spacing.

6. The method of claim 1 , wherein the inter-fin spacing between adjacent fins is filled by the gate dielectric and the gate conductor.

7. The method of claim 1 , further comprising forming a top spacer over the gate conductor after etching the gate conductor.

8. The method of claim 1 , further comprising forming top source/drain regions over the exposed top surfaces of the fins.

9. The method of claim 8 , wherein the top source/drain regions are formed by selective epitaxy.

10. The method of claim 8 , further comprising forming a top capping layer over the top source/drain regions.

11. The method of claim 1 , wherein the hard mask thickness over a first fin differs from the hard mask thickness over a second fin by at least 10%.

12. The method of claim 1 , wherein the hard mask thickness over a first region of a first fin differs from the hard mask thickness over a second region of the first fin by at least 10%.

13. The method of claim 1 , wherein the isotropic etching comprises wet etching.

14. A method of making a vertical FET device comprising:
forming a plurality of fins over a semiconductor substrate, wherein the fins define an inter-fin spacing between sidewalls of adjacent fins;
forming a hard mask over top surfaces of the fins;
forming a gate dielectric directly over the sidewalls of the fins and over sidewalls of the hard masks;
forming a gate conductor directly over the gate dielectric, wherein the gate conductor thickness is substantially equal to the inter-fin spacing; and
isotropically etching the gate conductor to form a functional gate, wherein isotropically etching the gate conductor decreases the gate conductor height to below the top surfaces of the fins.

15. The method of claim 14 , wherein the gate conductor height is 25% to 75% of the fin height.

Assignees

• Globalfoundries Inc

Inventors

• Bentley Steven
• Xie Ruilong

Classifications

• H10P50/667

  by liquid etching only · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/01326 Primary

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title