Vertical tunneling field effect transistor and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10164057-B1
Application number	US-201815878711-A
Country	US
Kind code	B1
Filing date	Jan 24, 2018
Priority date	Jun 2, 2017
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

First claim

What is claimed is:

1. A method of manufacturing a vertical tunnel field effect transistor (VTFET), the method comprising:
providing a fin structure protruding from a substrate and a first insulation layer such that the fin structure is embedded in the first insulation layer and a top surface of the fin structure is exposed by the first insulation layer;
removing the first insulation layer around the fin structure to partially expose side surfaces of the fin structure;
providing spacers on the partially exposed side surfaces of the fin structure;
epitaxially growing a source/drain structure the fin structure and between the spacers;
providing a capping layer to connect the spacers to each other to form an intermediate cap structure having a reverse-U shape, which covers top and side surfaces of the source/drain structure and top portions of the side surfaces of the fin structure;
removing the first insulation layer;
providing a gate insulation layer and a work function metal gate layer along the intermediate cap structure and the fin structure; and
partially removing the gate insulation layer and the work function metal gate layer to define a gate insulator and a metal gate under the intermediate cap structure.

2. The method of claim 1 , further comprising:
providing a separation pattern to surround bottom portions of the side surfaces of the fin structure, the separation pattern providing electrical isolation between the metal gate and a source/drain region formed in the substrate.

3. The method of claim 1 , wherein the providing the fin structure includes:
providing a sacrificial layer on the substrate;
patterning the sacrificial layer and the substrate to form a preliminary fin structure;
providing the first insulation layer to expose a top surface of the preliminary fin structure; and
removing the sacrificial layer to form the fin structure.

4. The method of claim 3 , wherein the providing the first insulation layer to expose the top surface of the preliminary fin structure includes,
forming the first insulation layer after the patterning the sacrificial layer and the substrate to form the preliminary fin structure, and
planarizing the first insulation layer until the top surface of the preliminary fin structure is exposed.

5. The method of claim 3 , further comprising:
providing an oxide hard mask layer on the sacrificial layer after providing the sacrificial layer on the substrate and before the patterning the sacrificial layer and the substrate to form the preliminary fin structure, and
wherein the patterning the sacrificial layer and the substrate to form the preliminary fin structure includes patterning the oxide hard mask layer together with the sacrificial layer and the substrate.

6. The method of claim 3 , wherein the sacrificial layer includes a material having an etch electivity to a material included in the first insulation layer.

7. The method of claim 1 , further comprising:
forming a contact hole through the intermediate cap structure to provide a final cap structure such that the final cap structure includes pillar portions which cover the side surfaces of the source/drain structure and cover the top portions of the side surfaces of the fin structure.

8. The method of claim 1 , wherein the epitaxially growing the source/drain structure includes:
epitaxially growing the source/drain structure beyond a top surface of the first insulation layer; and
removing the source/drain structure to a thickness such that a top surface of the source/drain structure is lower than the top surfaces of the spacers.

9. The method of claim 1 , wherein the providing the capping layer includes:
forming the capping layer on the first insulation layer, the spacers, and the fin structure; and
partially removing the capping layer to form the intermediate cap structure having the reverse-U shape.

10. The method of claim 1 , wherein the providing the spacers includes:
providing a second insulation layer on the first insulation layer and the fin structure, the second insulation layer having an etch selectivity with respect to the first insulation layer; and
etching the second insulation layer to form the spacers on the side surfaces of the fin structure that have been exposed by the partially removing the first insulation layer.

11. The method of claim 10 , wherein the first insulation layer includes an oxide material and the second insulation layer includes a nitride material.

12. The method of claim 10 , wherein the capping layer has an etch selectivity with respect to the second insulation layer and the work function metal gate layer.

13. The method of claim 10 , wherein the second insulation layer and the capping layer include a nitride material.

14. The method of claim 1 , further comprising:
forming a capping metal layer on the work function metal gate layer before the partially removing the gate insulation layer and the work function metal gate layer.

15. The method of claim 14 , wherein the capping metal layer includes at least one of TiAl, TiC, or TiAlC, and the work function metal gate layer includes TiN.

16. A vertical tunnel field effect transistor (VTFET) comprising:
a fin structure protruding from a substrate, the fin structure acting as a channel of the VTFET, the substrate including a source/drain region;
an epitaxially-grown source/drain structure on a surface of the fin structure;
a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure;
a gate insulator covering a remaining portion of the side surfaces of the fin structure under the pillar portions of the cap;
a work function metal gate on the gate insulator; and
a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region.

17. The VTFET of claim 16 , further comprising:
a capping metal gate on the work function metal gate, the capping metal gate extending in a direction parallel to a surface of the substrate.

18. The VTFET of claim 16 , wherein the cap includes an insulating material that has an etching selectivity with respect to the work function metal gate.

19. The VTFET of claim 16 , wherein the work function metal gate includes a vertical portion on the gate insulator and a horizontal portion on the separation pattern.

20. The VTFET of claim 19 , wherein the gate insulator includes a portion between the separation pattern and the horizontal portion of the work function metal gate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Kyung Yub
• Kwon Tae Yong
• Kwon Oh Seong
• Jeong Soo Yeon
• Park Yong Hee
• Yoo Jong Ryeol

Classifications

• H01L29/7827

  Electricity · mapped topic

• H01L29/1037

  Electricity · mapped topic

• H01L29/4238

  Electricity · mapped topic

• H01L29/66666 Primary

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic