Self aligned top extension formation for vertical transistors

Patent metadata

Field	Value
Publication number	US-2018114859-A1
Application number	US-201715626680-A
Country	US
Kind code	A1
Filing date	Jun 19, 2017
Priority date	Oct 24, 2016
Publication date	Apr 26, 2018
Grant date	—

Abstract

A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

First claim

1 . A semiconductor device comprising:
a first source/drain region of a doped semiconductor material on a supporting substrate; a vertically orientated channel region, wherein an extension of the first source/drain region is present at a first end of the vertically orientated channel region and includes a portion of the doped semiconductor material that provides the first source/drain region; an epitaxial uniformly doped extension region layer present at a second end of the vertically orientated channel region; and a second source/drain region on the epitaxial uniformly doped extension region layer, wherein the epitaxial uniformly doped extension region layer is a separate layer from the vertically orientated channel region and the second source/drain region.

2 . The semiconductor device of claim 1 , wherein the supporting substrate includes as punch through stop layer over a type IV semiconductor base.

3 . The semiconductor device of claim 1 , further comprising a gate structure on the vertically orientated channel region and separated from the first source/drain region by a first dielectric spacer layer, and separated from the second source/drain region by a second dielectric spacer layer.

4 . The semiconductor device of claim 1 , wherein the a dopant concentration that provides the conductivity type of the epitaxial uniformly doped extension region layer is less than a dopant concentration that provides the conductivity type of the second source/drain region.

5 . The semiconductor device of claim 1 , wherein the epitaxial uniformly doped extension region layer is composed of a different base semiconductor material than the vertically orientated channel region.

6 . The semiconductor device of claim 1 , wherein the epitaxial uniformly doped extension region layer is composed of a same base semiconductor material than the vertically orientated channel region.

7 . The semiconductor device of claim 1 , wherein the epitaxial uniformly doped extension region layer is at a depth at and below the second dielectric spacer.

8 . The semiconductor device of claim 1 , wherein the epitaxially uniformly doped extension region layer has a thickness ranging from 1 nm to 10 nm.

9 . The semiconductor device of claim 1 , wherein the semiconductor device is a vertical field effect transistor.

10 . A semiconductor device comprising:
a first source/drain region of a first semiconductor material on a supporting substrate; a vertically orientated channel region, wherein an extension of the first source/drain region is present at a first end of the vertically orientated channel region and includes a portion of the first semiconductor material that provides the first source/drain region, the extension of the first source/drain region and the vertically orientated channel region having a same width; an epitaxial uniformly doped extension region present at a second end of the vertically orientated channel region; and a second source/drain region on the epitaxial uniformly doped extension region, wherein the epitaxial uniformly doped extension region is a separate layer from the vertically orientated channel region and the second source/drain region.

11 . The semiconductor device of claim 10 , wherein the supporting substrate includes as punch through stop layer over a type IV semiconductor base.

12 . The semiconductor device of claim 10 , further comprising a gate structure on the vertically orientated channel region.

13 . The semiconductor device of claim 12 , the gate structure being separated from the first source/drain region by a first dielectric spacer layer, and separated from the second source/drain region by a second dielectric spacer layer.

14 . The semiconductor device of claim 10 , wherein the a dopant concentration that provides the conductivity type of the epitaxial uniformly doped extension region layer is less than a dopant concentration that provides the conductivity type of the second source/drain region.

15 . The semiconductor device of claim 10 , wherein the epitaxial uniformly doped extension region layer is composed of a different base semiconductor material than the vertically orientated channel region.

16 . The semiconductor device of claim 10 , wherein the epitaxial uniformly doped extension region layer is composed of a same base semiconductor material than the vertically orientated channel region.

17 . The semiconductor device of claim 13 , wherein the epitaxial uniformly doped extension region layer is at a depth at and below the second dielectric spacer.

18 . The semiconductor device of claim 10 , wherein the epitaxially uniformly doped extension region layer has a thickness ranging from 1 nm to 10 nm.

19 . The semiconductor device of claim 10 , wherein the semiconductor device is a vertical field effect transistor.

20 . A semiconductor device comprising:
a vertically orientated channel region; a first source/drain region present at a first end of the vertically orientated channel region; an epitaxial uniformly doped extension region present at a second end of the vertically orientated channel region; and a second source/drain region present on the epitaxial uniformly doped extension region, wherein the epitaxial uniformly doped extension region is a separate layer from the vertically orientated channel region and the second source/drain region.

Assignees

• IBM

Inventors

• Gluschenkov Oleg
• Mehta Sanjay C
• Mochizuki Shogo
• Reznicek Alexander

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/208

  of electrically inactive species · CPC title